Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Input I-V and sampling time characteristics ofthe ACT device

The input I-V and sampling-time characteristics of the acoustic charge transport (ACT) device are presented for ohmic-contact charge injection and Schottky-gate-modulated charge injection. A computationally efficient analysis technique is developed to calculate the I-V and sampling-time data from two-dimensional potential and carrier-density distributions. Device physics and architecture are incorporated into the analysis through a numerical charge-injection model which is used to compute the potential and carrier-density distributions. Theoretical results are presented to demonstrate the charge injection characteristic of some typical device structures. The effects that the injection method, the epitaxial layer structure and the acoustic wave amplitude have on device performances are discussed. The physical basis of the analysis enables it to be used to study several other design parameters. Experimental measurements of a device I-V and input transconductance show good agreement with calculated data. This analysis technique provides a means of assessing the performance potential of new device designs     

Electrical characterization and modeling of alternating-currentthin-film electroluminescent devices

Electrical characterization of evaporated ZnS:Mn alternating-current thin-film electroluminescent (ACTFEL) devices is accomplished by capacitance-voltage (C-V) analysis. Interpretation of these C-V characteristics is aided by SPICE modeling and by electrical characterization of an ideal ACTFEL device constructed from discrete components, based on a simple equivalent circuit for the ACTFEL device. Various features of the C -V curve are ascribed to equivalent circuit parameters and associated device physics parameters     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs

The usual approximate expression for measured f_T =[g_m/2π (C_gs+C _gd)] is inadequate. At low drain voltages just beyond the knee of the DC I-V curves, where intrinsic f _t is a maximum for millimeter-wave MODFETs, the high values of C_gd and G_ds combine with the high g_m to make terms involving the source and drain resistance significant. It is shown that these resistances can degrade the measured f_T of a 0.30-μm GaAs-AlGaAs MODFET from an intrinsic maximum f_T value of 73 GHz to a measured maximum value of 59 GHz. The correct extraction of maximum f_T is essential for determining electron velocity and optimizing low-noise performance     

Surface-charge properties of fluorine-doped lead borosilicate glass

Surface-charge configurations, together with stability under bias-temperature (BT) stress, for F-doped and Na-doped lead borosilicate glass were investigated by using C-V and I- V measurements on metal-glass-silicon capacitors and on diodes passivated with the glass. The C-V characteristics showed an increase in negative charge for F doping and in positive charge for Na doping. Alkali impurities in the glass mainly controlled the surface-charge shift during BT, but additional changes, similar to those for Na doping but reversing the sign of the charge, took place by F doping. The leakage current decrease in the diode passivated with F-doped glass, which contradicts the results of C-V measurement, may be due to the education of the generation current by the interaction between the silicon surface and F^- ions     

SPICE macro model for the simulation of zener diodeI-V characteristics

The problems encountered when using the existing SPICE diode model to represent the I-V characteristics of a Zener diode in the reverse region are examined. A Zener diode macro model that has accurate I-V simulation characteristics and can be easily constructed using SPICE-provided primitives is presented. The static I-V characteristics and temperature response of the diode are reviewed. The performance of the model is discussed, and its main enhancements as compared to the SPICE model are identified     

An analytical model for I-V and small-signalcharacteristics of planar-doped HEMTs

An analytical current-voltage (I-V) model for planar-doped HEMTs is developed. This compact model covers the complete range of I-V characteristics, including the current saturation region and parasitic conduction in the electron-supplying layer. Analytical expressions for the small-signal parameters and current-gain cutoff frequency are derived from the I-V model. Modeling results for a 0.1-μm-gate planar-doped AlInAs-GaInAs HEMT show excellent agreement with measured characteristics. Threshold voltages and parasitic conduction in planar-doped and uniformly doped HEMTs are also compared and discussed     

A new method of determination of the I-Vcharacteristics of negative differential conductance devices

A method for mapping the complete I-V characteristic of a negative differential conductance (NDC) device has been investigated. This method employs the measurable positive differential conductance (PDC) portions of the DC I-V curve together with the measured conductances at a fixed DC bias voltage in the PDC region with different RF signal levels using a standard semiconductor analyzer. The NDC regime of the I-V curve is numerically constructed from the measured conductances at a fixed DC bias voltage in the PDC region with different signal levels using a large-signal nonlinear-circuit analysis     

A new technique to determine the average low-field electronmobility in MESFET using C-V measurement

A method to determine the average low-field mobility using the number of electrons available for the conduction based on C-V measurement is proposed. This technique requires neither information of the doping profile in the channel, nor the exact value of the threshold voltage. For a D-mode MESFET, the average electron mobility magnitude is compared with that of the C. Chen and D.K. Arch (1989) method. The technique to determine the average electron mobility in the channel described is much simpler. Based on C- V measurement, good agreement is obtained between experimental data and simulation calculation for the electron density in the channel. Using the proposed method, the dependence of average electron mobility on the gate voltage is also proposed. Using the proposed method for determining the average electron mobility, the effect of a p-buried layer on the mobility was investigated, and is in good agreement with the physical phenomena     

PV module characterization using Q-Rdecomposition based on the least square method

The determination of solar cell parameters (I-V characteristic) from experimental data was achieved by using the Q -R decomposition technique based on the least squares method, where all data points were considered. The algorithm used a three-parameter equation transformed from the original cell equation of five parameters. This method could be used to analyze the I-V characteristics of photovoltaic (PV) modules of various technologies under the natural conditions of implementation, and to help to establish the best sizing of a PV system and the best adaptation of a PV system to its environment     

A new method of determination of the I-Vcharacteristics of negative differential conductance devices bymicrowave reflection coefficient measurements

A technique to map out all of the I-V characteristics of negative differential conductance (NDC) devices is described. This method uses the DC measurable positive conductance portions of the I-V curve together with the measured microwave reflection coefficients at different RF signal levels and fixed DC bias voltage. The advantages of the method for high NDC devices are pointed out in a stability analysis. The complete I-V curve of a tunnel diode has been obtained with an accuracy within 5% in a proof-of-principal test of this method     

Unusual C-V profiles of Si-implanted (211) GaAssubstrates and unusually low-noise MESFETs fabricated on them

The C-V profiles of ion-implanted (211) substrates show unusual non-Gaussian characteristics. MESFETs fabricated on these substrates have unusually low noise figures of less than 1.0 dB at 12 GHz. These devices are superior to most devices fabricated on the traditional (100) orientation, and even compare very favorably to commercial HEMTs (high-electron-mobility transistors)     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

A new technique for determining the generation lifetime profile inthin semiconductor films with application to silicon-on-insulator (SOI)substrates

A differential technique which uses reverse-biased current-voltage (I-V) and capacitance-voltage (C-V) measurements on a p-n junction or a Schottky barrier diode for determining the generation lifetime profile in thin semiconductor films is discussed. It is shown that the bias-independent current can be eliminated by this differential technique. Furthermore, any error caused by field-enhanced current can be estimated. This method has been used to determine the generation lifetime profile in thin silicon epitaxial film grown on SIMOX substrates     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Light-to-input nonlinearities in an R-LED series network

The light-to-current (L-I) and light-to-voltage (L-V) differential nonlinearities in the simple network of a customary LED and an external resistor R in series are analyzed and calculated theoretically and compared with experimental data. Particular emphasis is placed on the influence of the log-arithmetic slope ν of the L-I characteristic and the bias current I upon the ratio of the corresponding nonlinearity parameters. It is thus deduced that, for a given optical power P, over superlinear portions of the L-I curve (ν>1) the L-I linearity is typically better than its corresponding L-V linearity. On the contrary, when the L-I dependence is sublinear (ν<1) the voltage driving scheme may ensure for the R-LED network, or the LED alone, a local L-V response much more linear than the L-I response, provided that appropriate (optimum) I and/or R values are chosen     

Single barrier varactors for submillimeter wave power generation

Theoretical work on single barrier varactor (SBV) diodes indicates that the efficiency of a tripler with a SBV diode has a maximum for a considerably smaller capacitance variation than previously thought. SBV diodes based on GaAs, InGaAs and InAs have been fabricated and their DC properties have been tested. Detailed modeling of the carrier transport properties of the SBV device is carried out in two steps. First, the semiconductor transport equations are solved simultaneously, using a finite difference scheme in one dimension. Second, the calculated I -V and C-V characteristics are used by a multiplier simulator to calculate the optimum impedances and output powers at the frequencies of interest. The authors have developed an analysis technique which complements the harmonic balance technique. Simulations for a case study of a 750-GHz multiplier show that InAs diodes perform favorably compared to GaAs diodes