InSyn: integrated scheduling for DSP applications

We present the InSyn algorithm for high-level synthesis of DSP applications. InSyn combines allocation and scheduling of functional, storage, and interconnect units into a single phase and uses the following unique optimizations. (i) The concept of register states (free, busy, and undecided) is used for optimizing registers in a partial schedule where lifetimes of data values are not yet available. (ii) Reusable data values and broadcast are used to alleviate bus contention. (iii) InSyn can alternate between performance-guided and resource-guided measures. For example, InSyn can forgo its priority in favor of completing partially evaluated paths when the availability of allocated registers becomes low. (iv) InSyn ran selectively increase execution time of noncritical operations to alleviate bus contention. (V) InSyn can optimize and trade off distinct (functional units, interconnect, and registers) resource sets concurrently leading to more area-delay efficient designs. (vi) InSyn utilizes estimation tools towards resource allocation, design space pruning, and evaluation of synthesized designs. The experiments show that the features incorporated in inSyn result in very good designs     

Resource-constrained loop list scheduler for DSP algorithms

We present a new algorithm for resource-constrained scheduling for digital signal processing (DSP) applications when the number of processors is fixed and the objective is to obtain a schedule with the minimum iteration period. This type of scheduling is best suited for moderate speed applications where conservation of area and power is more important than speed. We define and make use of newgraph dependent constraints to obtain a lower bound estimate on the iteration period for any data-flow graph. By satisfying these constraints before performing the scheduling task, we can restrict the design space and can generate valid schedules in less time than previously reported. The graph dependent constraints provide a more accurate lower bound estimate on the iteration period than previously published results. This new scheduling algorithm exploits the iterative nature of DSP algorithms and uses aniterative-loop based scheduling approach. This resource scheduling algorithm has been incorporated in the Minnesota ARchitecture Synthesis (MARS) system. Our approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining to generate optimal and near optimal schedules.This research was supported by the Advanced Research Projects Agency under grant number F33615-93-C-1309 and the office of Naval Research under contract number N00014-91-J-1008.     

VLIW DSP for mobile applications

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented     

Energy-efficient approximate adders for DSP applications

In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence virtuoso tool under 45 nm CMOS technology. Supply voltage is?+?0.5 V.

     

Efficient unfolding procedure for DSP applications

An FSFG can be used to obtain a rate-optimal schedule. There are some criteria to measure the optimality. Normally, an iteration period bound (IPB) is used for the optimal implementation. If an iteration period (IP) is the same as the IPB, the schedule is called rate-optimal. Unfolding can reduce the IP and guarantee rate-optimal schedules with an optimum unfolding factor. A new unfolding procedure, called JK's unfolding, is introduced which has low complexity and can be described using graphical methods     

Amplitude-locked loop analysis for calibration applications

A linear analysis of an ALL, as it would be used in an amplitude calibration, is presented. The impact of different loop filter choices is considered, for steady-state error and loop dynamics as well as for disturbances in the input amplitude and peak detector ripple. It is shown that in most applications a loop filter with an integrator is desirable.     

Optical networks for local loop applications

Some of the options for optical technology within the local loop environment are examined. In particular, passive shared access networks have been considered in some detail. These networks show great promise for delivering existing telephone services to small to medium business customers (4-30 lines) economically by the early 1990s. Extending fiber to the home will also be possible by virtue of a similar passive network infrastructure for customers requiring new broadband services beyond the single telephone line. For one-line plain old telephone service (POTS) customers, an intermediate approach of terminating the fiber network at the final network distribution point, with copper retained for the final leg, may be used prior to the provision of broadband services. A key feature of the passive optical network architecture is the use of wavelength-division multiplexing (WDM) as an upgrade strategy, allowing graceful upgrading from telephone services to multichannel high-definition television (HDTV) on gigabit/second bearers and full two-way switched broadband services employing wavelength routing across the network     

Adaptive rate-controlled scheduling for multimedia applications

We present a framework for integrated scheduling of continuous media (CM) and other applications. The framework, called ARC scheduling, consists of a rate-controlled on-line CPU scheduler, an admission control interface, a monitoring module, and a rate adaptation interface. ARC scheduling allows threads to reserve CPU time for guaranteed progress. It provides firewall protection between threads such that the progress guarantee to a thread is independent of how other threads actually make scheduling requests. Rate adaptation allows a CM application to adapt its rate to changes in its execution environment. We have implemented the framework as an extension to Solaris 2.3. We present experimental results which show that ARC scheduling is highly effective for integrated scheduling of CM and other applications in a general purpose workstation environment. ARC scheduling is a key component of an end system architecture we have designed and implemented to support networking with quality of service guarantees. In particular, it enables protocol threads to make guaranteed progress     

Phase-locked loop design for on-chip tuning applications

A novel phase-locked loop scheme is proposed, the main application of which is in on-chip tuning circuits. It involves the use of a variable gain amplifier and also a frequency tunable loop filter, providing infinite hold-in range, a fractionally constant pull-out range and also a fractionally constant ripple     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

DSP应用青睐实时操作系统

ＤＳＰ应用习惯上采用人工优化的汇编代码。然而,由于ＤＳＰ应用趋于复杂化,使用高级语言亦很普遍,促使开发者目前多采用实时操作系统(ＲＴＯＳ)。为了满足开发者的需求,ＤＳＰ供应商和第三方ＲＴＯＳ厂商已发布了ＤＳＰ芯片专用的操作系统。     

Compact current-mode loop filter for PLL applications

A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I/sub cp2//(I/sub cp2/-I/sub cp1/), rather than the scaling ratio I/sub cp2//I/sub cp1/. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor R/sub G/.     

An efficient network-switch scheduling for real-time applications

Bursts consist of a varying number of asynchronous transfer mode cells corresponding to a datagram. Here, we generalized weighted fair queueing to a burst-based algorithm with preemption. The new algorithm enhances the performance of the switch service for real-time applications, and it preserves the quality of service guarantees. We study this algorithm theoretically and via simulations.     

Coprocessor for accelerated bit-true simulation of DSP applications

Bit-true simulation in DSP applications is very time consuming in comparison to functional-true simulation. This is caused by discrepancies in the finite word length features between the application and the simulating processor. The authors present a method for accelerating bit-true simulation based on coprocessor with dedicated instructions     

Design of low-error fixed-width multiplier for DSP applications

A low-error design of the fixed-width parallel multiplier for digital signal processing (DSF) applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit, product with lower relative product errors, but uses only about half the area of a standard parallel multiplier. These features make it very suitable for use in many DSP applications such as arithmetic coding, wavelet transformation, digital filtering     

一种新型的适用于数字信号处理的FPGA架构研究

本文提出了一种适用于数字信号处理的FPGA结构,该结构能容易的嵌入DSP模块使得在应用于数字信号处理时FPGA的性能得以改善。除了整体结构,本文提出了一种改进的2级多路选择器。 通过在传统2级多路选择器添加SLEEP MODE路径,降低了其静态功耗。此外,本文在长线中途驱动处添加了缓冲器, 使得长线的延迟降低了9.8%,而面积只增加了4.7%。该结构已经成功流片,采用的是标准的0.13um工艺,裸片面积为6.3 × 4.5mm2,采用QFP208封装。与传统FPGA相比,常用DSP模块测试例子的性能提高了28.6% ~ 302%     

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented.DSP modules can be inserted into FPGA conveniently with the proposed architecture,which is much faster when used in the field of digital signal processing compared with traditional FPGAs.An advanced 2-level MUX(multiplexer) is also proposed.With the added SLEEP MODE PASS to traditional 2-level MUX,static leakage is reduced.Furthermore, buffers are inserted at early returns of long lines.With this kind of buffer,the delay of the long line is improved by 9.8%while the area increases by 4.37%.The layout of this architecture has been taped out in standard 0.13μm CMOS technology successfully.The die size is 6.3×4.5 mm~2 with the QFP208 package.Test results show that performances of presented classical DSP cases are improved by 28.6%-302%compared with traditional FPGAs.     

LED spectral slicing for single-mode local loop applications

An approach towards a single-mode local loop is presented in which each customer is given a dedicated wavelength channel by taking different wavelength slices from identical LEDs. This is accomplished by means of wavelength division multiplexing (WDM) components. Results from a four-channel system operating at 2 Mbit/s over 2.2 km, together with a theoretical analysis of a ten-channel system, are presented