Logic programming and compiler writing

The concept of ‘logic programming’, and its practical application in the programming language Prolog, are explained from first principles. The ideas are illustrated by describing in detail one sizable Prolog program which implements a simple compiler. The advantages and practicability of using Prolog for ‘real’ compiler implementation are discussed.     

VLIW处理器的设计与实现

介绍了基于FPGA实现VLIW微处理器的基本方法,对VLIW微处理器具体划分为5个主要功能模块.依据FPGA的设计思想,采用自顶向下和文本与原理图相结合的流水线方式的设计方法,进行VLIW微处理器的5个模块功能设计,从而最终实现VLIW微处理器的功能,并进行了板级功能验证.     

分簇结构超长指令字DSP编译器的设计与实现

超长指令字（VLIW）是高端DSP普遍采用的体系结构。VLIW DSP在硬件上没有调度和冲突判决的机制，其性能的发挥完全依靠编译嚣的优化效果．基于可重定向编译基础设施IMPACT，为分簇VLIW DSP YHFT—D4设计与实现了优化编译器．其中着重讨论了可重定向信息的定义、代码注释、SIMD指令的支持、分簇寄存器分配以度指令级并行开发和资源冲突解决等内容．实验结果表明该编译器可以达到较好的优化效果．     

面向VLIW处理器的GAS汇编器实现

DSP处理器采用VLIW结构提高了指令级并行度,同时也增加了为其开发汇编器的难度.本文在汇编器GAS(GNV Assemblor)的基础上,讨论了为VLIW结构DSP开发汇编器的关键技术.该技术通过分析汇编指令的串并行信息为DSP产生指令包;通过相关性检查改善了代码膨胀问题,在保证汇编器功能正确的同时,提高了性能.     

VLIW结构处理器执行部件的设计与实现

本文介绍了一种超长指令字（VLIW）结构的处理器执行部件（ALU）的结构和实现，并对其中一些优化设计的技术进行了讨论，这些技术主要包括共享端口减少模块的输入输出端口数，平均分配各级流水线负担以提高主频，相似操作集中以优化设计等等。     

A novel compiler support for automatic parallelization on multicore systems

The widespread use of multicore processors is not a consequence of significant advances in parallel programming. In contrast, multicore processors arise due to the complexity of building power-efficient, high-clock-rate, single-core chips. Automatic parallelization of sequential applications is the ideal solution for making parallel programming as easy as writing programs for sequential computers. However, automatic parallelization remains a grand challenge due to its need for complex program analysis and the existence of unknowns during compilation. This paper proposes a new method for converting a sequential application into a parallel counterpart that can be executed on current multicore processors. It hinges on an intermediate representation based on the concept of domain-independent kernel (e.g., assignment, reduction, recurrence). Such kernel-centric view hides the complexity of the implementation details, enabling the construction of the parallel version even when the source code of the sequential application contains different syntactic variations of the computations (e.g., pointers, arrays, complex control flows). Experiments that evaluate the effectiveness and performance of our approach with respect to state-of-the-art compilers are also presented. The benchmark suite consists of synthetic codes that represent common domain-independent kernels, dense/sparse linear algebra and image processing routines, and full-scale applications from SPEC CPU2000.     

A compiler infrastructure for embedded heterogeneous MPSoCs

Programming heterogeneous MPSoCs (Multi-Processor Systems on Chip) is a grand challenge for embedded SoC providers and users today. In this paper, we argue the need for and significance of positioning the language and tool design from the perspective of practicality to address this challenge. We motivate, describe and justify such a practical design of a compilation framework for heterogeneous MPSoCs targeting the domain of streaming applications, named MAPS (MPSoC Application Programming Studio). MAPS defines a clean, light-weight C language extension to capture streaming programming models. A retargetable source-to-source compiler is developed to provide key capabilities to construct practical compilation frameworks for real-world, complex MPSoC platforms. Our results have shown that MAPS is a promising compiler infrastructure that enables programming of heterogeneous MPSoCs and increases productivity of MPSoC software developers.     

A transportable extendable compiler

This report describes the development of a transportable extendable self-compiler for the language SIMPL-T. SIMPL-T is designed as the base language for a family of languages. The structure of the SIMPL-T compiler and its transportable bootstrap are described. In addition, the procedures for generating a compiler for a new machine and for boot-strapping the new compiler on to the new machine are demonstrated.     

VLIW微处理器特征与编译技术支持

VLIW是一种早已出现但一直未能广泛使用而现今又被重新重点研究的微处理器设计思想与技术，它跟超标量技术一样支持每周期执行多条指令，但并行度更高。本文将详细介绍VLIW的概念及其发展历程，讨论VLIW微处理器的特征与所需的编译技术支持，并与超标量微处理器进行比较分析。     

Minivital: A compiler case study

This paper is the case study of a compiler for a very large language implemented for a minicomputer. Although the language is special purpose and perhaps not of general interest, the techniques used and the performance obtained make the compiler itself somewhat interesting.     

A pascal compiler for ICL 1900 series computers

The transport of a PASCAL compiler from a CDC 6000 series computer to an ICL 1900 series computer is reported, with some comments on the method used.     

面向多簇超长指令字DSP的向量化优化算法

BWDSP是一款针对高性能计算领域设计的处理器,采用多簇超长指令字（VLIW）体系结构和SIMD架构,同时也提供了很多向量化指令．然而现有的编译框架无法对这些向量化指令提供支持,因此本文提出了一种向量化优化算法,可以显著提高一些在DSP领域有着广泛应用的计算密集型程序的性能．最终实验结果表明,该优化算法能够平均取得6．60倍的加速比．     

A methodology and notation for compiler front end design

A methodology and associated notation for designing compiler front ends, and in particular the interface between the parser and the semantic routines, is described. The methodology leads to a clean, easy to understand, documentable design. The notation is similar to an attribute grammar, but its purpose is to document the first pass of a specific compiler, rather than to describe the semantics of a language. It is designed to be accessible to non-specialists, easy to learn, and natural. It can be used with or without software support. The notation was used during the development of a large compiler, and to assist in the transfer of the compiler to the group that will maintain it. Experience with the notation indicates that it meets its goals.     

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism (ILP) in applications has gone up considerably. However, monolithic register file VLIW architectures present scalability problems due to a centralized register file which is far slower than the functional units (FU). Clustered VLIW architectures, with a subset of FUs connected to any RF provide an attractive solution to address this issue. Recent studies with a wide variety of inter-cluster interconnection mechanisms have reported substantial gains in performance (number of cycles) over the most studied RF-to-RF type interconnections. However, these studies have compared only one or two design points in the RF-to-RF interconnects design space. In this paper, we extend the previous reported work. We consider both multi-cycle and pipelined buses. To obtain realistic bus latencies, we synthesized the various architectures and calculated post-layout clock periods. The results demonstrate that while there is less that 10% variation in interconnect area, the bus based architectures are slower by as much as 400%. Also, neither multi-cycle or pipelined buses nor increasing the number of buses itself is able to achieve performance comparable to point-to-point type interconnects.     

VLIW体系结构微处理器的一种设计方法

微处理器体系结构的发展经历了三个不同的阶段,以Intel早期X86产品为代表的CISC体系结构微处理器;以MIPS、PA-RISC、SPARC、ALPHA、PowerPC等为代表的RISC体系结构微处理器;以Intel近期产品为代表的CISC—RISC混合型体系结构微处理器。RISC和CISC由于其实现技术的复杂性,逐步退     

A LIS compiler for GCOS-7

This paper describes the implementation of a LIS compiler for GCOS-7. LIS is a high level system implementation language developed at CII-Honeywell Bull during the middle 1970s, and experience with the language and its implementation have largely influenced the design of Ada. The design of the compiler was particularly aimed at efficient code generation. Design decisions concerning the run-time organization in relation to procedure call and separate compilation are discussed. The structure of the compiler is described. The articulation between the different phases of the code generator is emphasized. Experience with the bootstrap is related.     

Dynamically Scheduling VLIW Instructions

Very long instruction word (VLIW) machines potentially provide the most direct way to exploit instruction-level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. In addition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or functional units with different latencies. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Preliminary measurements of the DTSVLIW performance, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.     

An analysis of Pascal programs in compiler writing

A method and results of static and dynamic analysis of Pascal programs are described. In order to investigate characteristics of large systems programs developed by the stepwise refinement programming approach and written in Pascal, several Pascal compilers written in Pascal were analysed from both static and dynamic points of view. As a main conclusion, procedures play an important role in the stepwise refinement approach and implementors of a compiler and designers of high level language machines for Pascal-like languages should pay careful attention to this point. The set data structure is one of the characteristics of the Pascal language and statistics of set operations are also described.     

面向嵌入式VLIW处理器的代码压缩技术

随着嵌入式系统的发展,在性能不断提高的同时,软件代码规模也不断扩大.而超长指令字结构更加引起了代码的膨胀,因此代码压缩技术变得很重要.本文基于自主研发的SDSP处理器核,应用3种压缩编码技术,比较它们压缩的效果,并讨论了包括压缩后地址的重映射以及解压缩结构的整体硬件方案.