Parallel realizations of distributed sample scramblers forapplications to cell-based ATM transmission

In this paper, a theory is developed in support of parallel realizations of the distributed sample scramblers (DSS) in the cell-based ATM transmission environment. For the relevant parallel realizations of the SRG (shift register generator) engines and the SRG sequence-generating circuits, the PSRG theory is applied which is readily available for parallel FSS (frame synchronous scrambler). For the synchronization of the parallel DSS, the double-sampling and double-correction schemes are employed as they efficiently match the two adjacently located sample conveyance channels within the ATM cells. The resulting synchronization conditions are described in terms of three theorems-one regarding the sampling time and vector's condition, and the other two regarding the correction time and vector's conditions for even- and odd-lengthened SRGs. Demonstration is given at the end on the use of the developed theory for parallel realizations of DSS in scrambling and descrambling the ITU-T recommended cell-based ATM signals     

Applications of sequence space and SRG theories to distributedsample scrambling

In this paper, we consider how to apply the sequence space and the shift register generator (SRG) theories to distributed sample scrambling (DSS), which exhibits the best performance in scrambling of small frame-sized signals. We first consider how to predict scrambling sequences using their samples, which is a basic problem for a proper synchronization within the DSS systems. Then for DSS scramblers, we consider how to determine the scrambler SRGs and the sampling times for conveying information on the scrambling sequence; and for DSS descramblers, we consider how to determine the descrambler SRGs, the correction times, and the correction vectors for a proper synchronization. We further examine how to realize the scramblers and the descramblers with minimized circuit complexity. Finally, we demonstrate how to apply the results to DSS scramblers and descramblers for application in cell-based asynchronous transfer mode (ATM) transmission     

Realizations of parallel and multibit-parallel shift registergenerators

We consider how to realize parallel shift register generators (PSRG) and multibit PSRGs, which can be directly used for parallel frame synchronous scrambling (FSS) in the bit- and multibit-interleaved multiplexing environments. We first describe the structure of PSRGs in terms of three parameters-the state transition matrix, the initial state vector, and the generating vectors. Then we discuss how to determine the three parameters of PSRGs that generate the desired parallel sequences in general. We further develop a method for the realization of minimum length PSRGs, and for the realization of PSRGs with minimized circuit complexity. Finally, we consider how to realize minimal PSRGs for use in multibit-parallel scrambling. The results are summarized in four sets of theorems, and are demonstrated through four examples     

Synchronization of shift register generators in general distributedsample scramblers

In this paper, a theory is developed to support the synchronization of shift register generators (SRGs) in the general class of distributed sample scramblers (DSSs). In the general DSS, the samples transmitted to the descrambler for its synchronization are freely generated out of the scrambler SRG, a special case of which is to take samples directly from the SRG sequence. To describe this general sampling method, the concept of sampling vectors is introduced. The delayed sample-transmission problem, which is a real problem in practical transmission systems, can be resolved by adopting the sampling vectors. This paper provides a systematic solution to the synchronization problem of the general DSS based on mathematical modeling. It first considers the sampling problem of the SRG state information, and then discusses the correction problem of the descrambler SRG state using the transmitted samples. Applications are attached at the end to demonstrate the developed theory for simple realizations of the DSS for use in the cell-based ATM transmission environment     

ATM的扰码技术(Ⅱ)

扼要地介绍了扰码的基本概念，但对在ＰＤＨ／ＳＤＨ以及以信元为基础的ＡＴＭ传输环境下的扰码技术作了重点的论述，指出了在以信元为基础的ＡＴＭ传输环境下所采用的ＤＳＳ扰码方案虽然复杂了一些，但它只进行一次扰码，并有一定的自由度，可以选择更适宜的扰码方案。     

ATM的扰码技术(Ⅰ)

扼要地介绍了扰码的基本概念，并重点地论述了在ＰＤＨ／ＳＤＨ以及以信元为基础的ＡＴＭ传输环境下的扰码技术，指出了在以信元为基础的ＡＴＭ传输环境下所采用的ＤＳＳ扰码方案，虽然复杂了一些，但可只进行一次扰码，并有一定的自由度，因此可以选择ＤＳＳ的扰码方案。     

International fixed satellite systems in synchronous digital hierarchy transport networks

This paper discusses functional and architectural aspects and suitable networks scenarios for the integration of international fixed satellite systems, such as the INTELSAT system, in and between digital networks implementing the new CCITT synchronous digital hierarchy (SDH). The paper presents SDH transmission network functional requirements, and combines them with current and anticipated future FSS operational requirements. It is shown that integration permits the use of SDH functions and features for enhanced network service provisioning by FSS in the international network fabric, and leads to new FSS system design criteria.     

双屏频率选择表面传输特性的研究

应用广义散射矩阵和矩量法对双屏圆环单元频率选择表面(Frequency Selective Surfaces简称FSS)、双屏Y环单元FSS和双屏Y孔单元FSS的传输特性进行了数值计算及分析.采用镀膜和光刻技术制备出相应单元图形的单屏FSS,利用精密装配技术将两单屏FSS进行装配,制备出相应的双屏FSS实验件;在微波暗室内用矢量网络分析仪测试了双屏FSS的传输系数,测试值与数值结果基本一致.结果表明:双屏FSS的传输系数曲线具有宽带宽和陡降截止的频率特性,其电磁散射特性较单屏FSS有很大的改善.     

Lightwave subscriber loop systems toward broad-band ISDN

The state-of-the-art of lightwave subscriber loop systems is reviewed. An approach is described for deriving an architecture for subscriber loop systems that can accommodate technological trends in broadband ISDN such as asynchronous transfer mode (ATM) and synchronous digital networks. Key component technology is discussed, namely, optical fibers and cables, splicing and connectors, and switching     

用FPGA实现ATM信元的字头处理

本文探讨了采用ＦＰＧＡ Ｘ３０００系列芯片实现独立于承载码流结构的ＡＴＭ信元字头处理器的可能性，针对ＦＰＧＡ处理速度相对低于可能的承载码流速率的问题，着重研究了字头ＨＥＣ字段生成，扰码，信元定界，解扰等过程的并行处理算法。     

100G以太网自同步并行扰码算法实现

扰码是在数字传输系统中,对于数字信息进行随机化处理的一种技术,被广泛应用于通信各个领域。首先介绍了扰码和自同步扰码的基本原理,通过对扰码原理的分析,实现了一种任意特征多项式、任意N位并行自同步扰码算法,并可演算得到任意特征多项式、任意N位并行帧同步扰码算法。该方法采用递推的方法直接得出N个时钟周期后编码器的状态值与当前编码器状态值之间的逻辑关系。其逻辑运算速度快且实现简单,十分有利于硬件实现。然后研究了基于802.3ba未来100G以太网中640bits自同步扰码算法的FPGA实现,给出了组合逻辑实现和时序逻辑实现两种方案,并对两种方案进行了对比分析,最后给出了640bits并行扰码器实现资源需求分析。     

高空间分辨率大视场遥感相机图像的高速高可靠传输系统研究

提出一种适于高空间分辨率大视场遥感相机的图 像高速高可靠传输系统。首先,分析了TLK2711的通信链路,提出 了基于同步控制字的高速串行传输策略;深入分析了噪声对传输可靠性的影响,进而提出(17,6)纠错编码算法,分析了纠错编码在大视场空间相机中应用的可行性; 最后,在某大视场TDICCD空间相 机样机上进行了系统测试。实验表明,本文系统可以实时传输80路高 量化数据,整个系统有 效数据吞吐率可达13.02Gbit/s;所 提出的(17,6)纠错编码算法纠错能力强,运算速度快,易于硬件 实现,每512Byte数据可纠正32bit的错误,提高了空间 相机高速串行传输的可靠性;系统在不同的传输速度下工作均表现出令人满意的效果。     

一种基于稀疏矩阵的多核并行扰码方法

针对多核环境中高速无线信号的加扰、解扰,提出了一种基于稀疏矩阵的多核并行扰码方法。首先对输入信号进行串/并转换,并将各路信号分别送入对应的处理器核;考虑基于稀疏矩阵的并行扰码生成器,在单个处理器核内,将其生成的伪随机码与输入信号进行模二加运算,得到单路信号的扰码输出;最后将多路并行的扰码输出变换为串行输出。运算量分析结果表明,采用IEEE 802.11n中的扰码生成多项式,与普通矩阵乘法实现的多核并行扰码方法相比,基于稀疏矩阵的多核并行扰码方法,其运算量降低了一个数量级。     

Error correction and error detection techniques for wireless ATM systems

Error correction and error detection techniques are often used in wireless transmission systems. The Asynchronous Transfer Mode (ATM) employs Header Error Control (HEC). Since ATM specifications have been developed for high‐quality optical fiber transmission systems, HEC has single‐bit error correction and multiple‐bit error detection capabilities. When HEC detects multiple‐bit error, the cell is discarded. However, wireless ATM requires a more powerful Forward Error Correction (FEC) scheme to improve the Bit Error Rate (BER) performance resulting in a reduction in the transmission power and antenna size. This concatenation of wireless FEC and HEC of the ATM may effect cell loss performance. This paper proposes error correction and error detection techniques suitable for wireless ATM and analyzes the performance of the proposed schemes. This revised version was published online in June 2006 with corrections to the Cover Date.     

基于TMS320F28335的永磁同步电动机控制器的设计

针对永磁同步电机（PMSM）具有结构简单、效率高、功率因数高等优点,研究和设计了一款以浮点型TMS320F28335数字信号处理器（DSP）为控制核心的永磁同步电机控制器。该控制器设计了三相全控桥式功率驱动电路和过流、欠压检测,温度监控等检测保护电路。能通过CAN总线连接外部显示模块以及RS232通信接口与上位机的高速通信并进行实时数据交换,软件部分采用空间矢量算法实现电流、速度和位置的精确控制。实验结果表明,控制器精度高、响应快、控制效果稳定。     

An overview of very high capacity transmission technology for NTT networks

This paper describes very high capacity optical transmission system technology, which is useful for long-haul trunk lines, and has led to the feasibility of NTT's first gigabit-per-second range transmission system. It also describes various devices and circuits, such as high performance lasers, photodetectors, very wide-band amplifiers, and high speed logic circuits required for the development of such systems. It then discusses future research areas and trends in advanced lightwave communication systems.     

新型副镜并联调整机构非线性特性及校正

为满足望远镜副镜结构定位精度的要求,提出一种固定杆长杆端轴向平移运动模式的六杆并联机构。从微分几何的观点研究了该机构输入关节空间向量与输出工作空间向量之间的非线性运动学特性,并采用曲率概念度量解轨迹的非线性弯曲。通过与雅可比矩阵的对比分析可知,采用曲率度量并联机构的非线性和采用雅克比矩阵反映的瞬时线性性质一致,所设计的副镜并联调整机构在整个运动行程范围内的最大非线性误差约为3.15 μm。测试结果表明:采用多项式误差曲线拟合校正之后,该副镜调整机构三维平移重复定位精度小于2.6 μm,二维旋转重复定位精度小于1.8″,满足实际望远镜观测的需要,采用的曲率度量法也可以为其他并联机构的非线性分析和校正提供一种新的思路。     

Space Vector Based Hybrid PWM Techniques for Reduced Current Ripple

This paper investigates certain novel switching sequences involving division of active vector time for space vector based pulsewidth modulation (PWM) generation for a voltage source inverter. This paper proposes two new sequences, and identifies all possible sequences, which result in the same average switching frequency as conventional space vector PWM (CSVPWM) at a given sampling frequency. This paper brings out a method for designing hybrid PWM techniques involving multiple sequences to reduce line current ripple. The three proposed hybrid PWM techniques (three-zone PWM, five-zone PWM and seven zone PWM) employ three, five and seven different sequences, respectively, in every sector. Each sequence is employed in a spatial region within the sector where it results in the lowest rms current ripple over the given sampling period. The proposed techniques lead to a significant reduction in THD over CSVPWM at high line voltages. The five-zone technique results in the lowest THD among real-time techniques with uniform sampling, while the seven-zone technique is the best among real-time techniques with twin sampling rates. The superior harmonic performance of the proposed techniques over CSVPWM and existing bus-clamping PWM techniques is established theoretically as well as experimentally.     

The asynchronous transfer mode: is it a waste of space?

The author discusses asynchronous transfer mode (ATM); a mechanism which permits the creation of new multimedia communication systems. It is the first transfer mode that permits high-speed transmission of real-time services and computer data simultaneously. The introduction of ATM to broadband-ISDN networks is discussed following its approval by the ITU-T. There are unresolved management issues and some of these have important implications for the success of ATM networks