A new extraction algorithm for the metallurgical channel length ofconventional and LDD MOSFETs

A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract L_met not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

A capacitance-based method for experimental determination ofmetallurgical channel length of submicron LDD MOSFETs

A capacitance based method for determining L_met the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via two-dimensional numerical device simulation of MOSFETs with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting L_met of MOSFETs with gate oxides thinner than 100 Å is better than 110 Å. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of L_eff, the effective electrical channel length, from the drain current, L_met is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFETs of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The L_met and L_eff extracted from measured capacitance and drain current data are compared. Results showed that L _met is typically 700 to 1200 Å shorter for submicron MOS technologies, but it tracks with L_eff, i.e. a shorter L _met corresponds to a shorter L_eff     

A new method for extracting the channel-length reduction and thegate-voltage-dependent series resistance of counter-implanted p-MOSFETs

Based on the channel-resistance measurement, a new method for extracting the channel-length reduction (ΔL_jj) and the gate-voltage-dependent source/drain resistance (R_SD) of counter-implanted p-MOSFETs is proposed, in which the necessity of the applying substrate bias is demonstrated and an empirical relationship between poly-Si gate length (L_M) and device structure parameters for ΔL_jj extraction is provided. This is the first attempt to extract the basic parameters of counter-implanted p-MOSFETs with the LDD structure. Numerical analysis using two-dimensional (2-D) device simulator has been used to verify the proposed extraction method. Furthermore, an improved approach to extract R_SD is also presented. Both numerical analysis and experimental results show good accuracy of our proposed method     

DIBL considerations of extended drain structure for 0.1 μmMOSFET's

The drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2-D) device simulations in the tenth-micrometer regime. We found that the drain extension length must be kept at a minimum in order to reduce the transistor cell area and to improve the device transconductance, G_m . However, without decreasing the deep source/drain junction depth, the minimum value of which is basically limited by the ability to form a good low resistive silicide contact, charge sharing associated with a small extension length deteriorates the short channel behavior of the device, via DIBL, even if aggressive scaling of the gate oxide thickness and the junction depth of the drain extension were used. The solution to this dilemma would be elevating the source/drain area by selective epitaxy to form a shallow, low resistive silicided junction. We propose here a novel device structure using the elevated silicide-as-a-diffusion-source (E-SADS), which improves the DIBL-G_m tradeoff, eliminates the contact problem, and maintains a minimal cell areal increase     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

Measurements and modeling of MOSFET I-V characteristics withpolysilicon depletion effect

The authors study the degradation of MOSFET current-voltage (V-I) characteristics as a function of polysilicon gate concentration (N_p ), oxide thickness (t_ox) and substrate impurity concentration (N_D) using measured and modeled results. Experimentally it is found that for MOSFETs with thin gate oxide (t_ox≈70 Å) and high substrate concentration (N_D ≈1.6×10¹⁷ cm^-3) the reduction in the drain current I_DS can be as large as 10% to 20% for devices with insufficiently doped polysilicon gate (5×10¹⁸ ⩽N_p⩽1.6×10¹⁹ cm^-3). Theoretically it is shown that the drain current degradation becomes more pronounced as N_p decreases, t_ox decreases, or N_D, increases. A modified Pao-Sah model that takes into account the polysilicon depletion effect and an accurate gate-field-dependent mobility model are used to compute I-V characteristics for various values of N_p, t_ox, and N_D. Good agreement between experimental and modeled results is observed over a wide range of devices     

Self-aligned control of threshold voltages in sub-0.2-μm MOSFETs

We propose a new method to control the threshold voltages (V_th) in sub-0.2 μm MOSFETs. The method suppresses V_th fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the V_th in numerous MOSFETs and show that our method can indeed suppress V_th fluctuations caused by variations in the fabricated gate length     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Experimental Method to Extract Effective Channel Length of Nanoscale n-MOSFETs

An experimental method of extracting the effective channel length L_eff from measured gate tunneling current (I_g) of nanoscale n-MOSFETs is proposed. The tunneling current from gate to the source and drain (I_gsd) was measured while applying a reverse bias to the substrate, and it was corrected for the depletion effect of the source/drain junctions. The gate tunneling current to the substrate (I_gc) was obtained by subtracting I_gsd from I_g. L_eff was calculated using a linear extrapolation of the I_gc versus gate length plot. The proposed method is a very simple and quite accurate method of extracting L_eff which does not require any additional assumptions and parameter extraction.     

A novel method for extracting the metallurgical channel length ofMOSFETs using a single device

A new charge-pumping method with dc source/drain biases and specified gate waveforms is proposed to extract the metallurgical channel length of MOSFETs by using a single device. Using two charge-pumping currents of a single nMOSFET measured under different V _GL (V_GH for pMOSFETs), the metallurgical channel length can be easily extracted with an accuracy of 0.02 μm. It is shown that the proposed novel method is self-consistent with the results obtained by the charge-pumping current measured from multidevices under different gate pulse waveforms and bias conditions     

双掺杂多晶Si栅MOSFET的截止频率研究

在前期对双掺杂多晶Si栅(DDPG)LDMOSFET的电场、阈值电压、电容等特性所作分析的基础上,仍然采用双掺杂多晶Si栅结构,以低掺杂漏/源MOS(LDDMOS)为基础,重点研究了DDPG-LDDMOSFET的截止频率特性.通过MEDICI软件,模拟了栅长、栅氧化层厚度、源漏区结深、衬底掺杂浓度以及温度等关键参数对器件截止频率的影响,并与相同条件下P型单掺杂多晶Si栅(p-SDPG)MOSFET的频率特性进行了比较.仿真结果发现,在栅长90 nm、栅氧厚度2 nm,栅极P,n掺杂浓度均为5×1019cm-3条件下,截止频率由78.74 GHz提高到106.92 GHz,幅度高达35.8%.此结构很好地改善了MOSFET的频率性能,得出的结论对于结构的设计制作和性能优化具有一定的指导作用,在射频领域有很好的应用前景.     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

A study on the physical mechanism in the recovery of gatecapacitance to Cox in implanted polysilicon MOSstructures

The anomalous CV characteristics of MOS capacitor structures with implanted n⁺ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO₂ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO ₂ gate dielectric should not present a serious problem in device reliability     

High-frequency dependence of channel noise in short-channel RFMOSFETs

Using a two-dimensional (2-D) Green's function technique, similar to Shockley's impedance field technique, simulation results of the drain i_d and gate induced i_g channel noise are presented for an nMOS transistor as a function of frequency. The simulation results show that for frequencies much lower than the cutoff frequency of the transistor f_t the correlation factor (i.e., i¯ _g¯i¯*_d¯/√i_g^-2 i_g^-2) between the drain and gate channel noise is equal to approximately 0.4j. For frequencies near the f_t of the device the correlation factor approximately equals 0.3j. For f/f_t~0.3, the contribution of the gate induced noise compared to the drain noise was found to be on the order of 1% (i.e., i _g^-2/i_d^-2(f_t/f) ²)     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

Ensemble Monte Carlo study of channel quantization in a 25-nmn-MOSFET

We develop a self-consistent, ensemble Monte Carlo device simulator that is capable of modeling channel carrier quantization and polysilicon gate depletion in nanometer-scale n-MOSFETs. A key feature is a unique bandstructure expression for quantized electrons. Carrier quantization and polysilicon depletion are examined against experimental capacitance-voltage (C-V) data. Calculated drain current values are also compared with measured current-voltage data for an n-MOSFET with an effective channel length (L_eff) of 90 nm. Finally, the full capabilities of the Monte Carlo simulator are used to investigate the effects of carrier confinement in a L_eff=25 nm n-MOSFET. In particular, the mechanisms affecting the subband populations of quantized electrons in the highly nonuniform channel region are investigated. Simulation results indicate that the occupation levels in the subbands are a strong function of the internal electric field configurations and two-dimensional (2-D) carrier scattering     

The effect of fluorine from BF2 source/drain extensionimplants on performance of PMOS transistors with thin gate oxides

Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF₂ is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 Å and gate lengths less than 0.5 μm