一种基于斜率-电阻相位插值的低功耗十倍频电路北大核心

基于65 nm CMOS工艺设计了一种低功耗低成本十倍频电路。在1.2 V电源电压下，电路功耗小于0.53 mW。提出了一种低复杂度的5段斜率-电阻相位插值方法，通过对四路正交斜率信号进行电阻相位插值，在8 MHz到24 MHz的输入频率范围内，实现了可重构的十倍频电路。该电路结构简单，仅包含正交方波信号发生器、斜坡信号发生器和提出的5段斜率-电阻相位插值器，可用于低功耗、低成本的倍频场合，且具有可接受的频率偏差。在输入频率为16 MHz,输入功率为-2.0 dBm时，电路输出功率为-12.9 dBm,倍频效率为4.40%。     

A 70-GHz fT low operating bias self-aligned p-type SiGeMODFET

A self-aligned process for the fabrication of SiGe p-type modulation-doped field-effect transistors (MODFETs) is described. Self-aligned devices with 0.1-μm gate-length have been fabricated and characterized. A maximum dc extrinsic transconductance of 258 mS/mm was obtained with a low turn-on resistance and very low knee voltage. Excellent high frequency performance with a unity current-gain cutoff frequency (f_T) of 70 GHz was obtained. This excellent high frequency performance was exhibited even at drain bias as low as 0.5 V     

Lasing characteristics for four-section MQW-DBR laser

A MQW-DBR laser with two active sections and low tuning efficiency has been developed. The device showed excellent lasing characteristics: a low threshold current of 10 mA, a high slope efficiency of 0.26 mW/mA, and a narrow linewidth of 280 kHz at P_out=15 mW. A red-shift carrier-induced FM response was obtained by nonuniform current injection to two active sections. A flat FM response with wide bandwidth (>2 GHz) was confirmed. The linewidth broadening due to wavelength tuning was suppressed through the reduction of tuning efficiency. A continuous tuning range of 0.8 nm was observed while maintaining the linewidth below 4 MHz     

一种分段温度补偿BiCMOS带隙基准源

设计了一种针对基准电压输出非线性的分段温度补偿电压基准源。该电路在基准源工作的低温和高温阶段对输出进行温度补偿,实现低温度系数。利用高增益的两级运算放大器以及增加PMOS管的栅长来提高电路的电源抑制比(PSRR)。在-55℃～125℃范围内,温度系数为2.9×10-6/℃,低频电源抑制比为-71dB。     

低相噪锁相介质振荡器研究

针对高的相位噪声指标要求,对取样锁相介质振荡器进行了研究.通过相位噪声分析,明晰了采用介质振荡器与取样锁相技术降低相位噪声的机理,并分别对介质振荡器与锁相环路进行了设计.设计中,应用HFSS与ADS对介质振荡器进行了联合仿真,体现了计算机辅助设计的优势.最终研制出17 GHz锁相介质振荡器,测试结果为:输出功率13.1 dBm;杂波抑制>70 dB;谐波抑制>25 dB; 相位噪声为-105 dBc/Hz@1 kHz,-106 dBc/Hz@10 kHz,-111 dBc/Hz@100 kHz,-129 dBc/Hz@1 MHz.     

Novel compact polarization converters based on ultra short bends

A novel integrated polarization converter based on ultra short bends is presented, which has a potential for low loss and small device size. A conversion value of 85% was experimentally measured with excess loss of 2.7 dB and overall dimensions of 975/spl times/83 /spl mu/m. Also 45% conversion was measured with extremely low excess loss of 0.4 dB for a device size of 760/spl times/86 /spl mu/m.     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

双音频率合成器的设计与实现

研究了一种输出双音信号、低相位噪声、低杂散的频率合成方法.该方法首先利用锁相环路分别产生两路信号,并通过优化设计环路滤波器改善输出信号相位噪声,进而利用设计的Wilkinson功率合成器将两路信号进行功率合成,并通过衰减和放大来控制双音信号功率.基于本方法研制实现的输出双音频率为2 015和2 020 MHz的频率合成器,输出功率范围-12～18 dBm,且连续可调,输出信号相位噪声优于-93 dBc/Hz@1 kHz,在输出功率4 dBm以下时,双音互调成分低于-50 dBc,可用于各种测试系统频率源,尤其便于对非线性系统的测试.     

Integratable, high speed buried ridge DFB lasers fabricated on semi-insulating substrates

The fabrication of buried ridge DFB lasers on semi-insulating substrates is described. A novel contacting mechanism was employed to give a series resistance of less than 4 Omega . Devices were fabricated at both 1.3 and 1.53 mu m with lasing thresholds as low as 16 mA. Single longitudinal mode operation was achieved with SMSR greater than 30 dB at both wavelengths. The structure gives an inherently low capacitance, which together with low threshold currents, low series resistance and fabrication on SI substrates makes these devices suitable for integration and high speed applications.<>     

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.     

Vacon变频器在提升机低频制动系统上的应用

本文介绍了矿井提升机制动要求,提出用低压变频器控制高压电机设计方案。低压变频器用于控制提升机实现低频制动时,需要控制变频器输出电压实现转矩控制,本文设计了P I D控制器,实现变频器的输出电压控制。给出了变频器低频制动控制系统结构,介绍了变频器软件程序的设计。试验结果表明,此低频制动系统具有较好的控制效果。     

A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads

A 25-ns 4-Mbit CMOS SRAM with 512 K word*8-bit organization has been developed. The RAM was fabricated using a 0.5- mu m double-poly and double-aluminum CMOS technology and was assembled in a 32-pin 400-mil DIP. A small cell size of 3.6*5.875 mu m/sup 2/ and a chip size of 7.46*17.41 mm/sup 2/ were obtained. A fast address access time of 25 ns with a single 3.3-V supply voltage has been achieved using the newly developed dynamic bit-line load (DBL) circuit scheme incorporated with an address transition detector (ATD), divided word-line structure (DWL), three-stage sense amplifier, and low-noise output circuit approach. A low operating current of 46 mA at 40 MHz and low standby currents of 70 mu A (TTL) and 5 mu A (CMOS) were also attained.<>     

一种低抖动低杂散的亚采样锁相环

设计了一个5.156 25 GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Dummy采样器和隔断缓冲器,进一步减小了压控振荡器对杂散的恶化。该亚采样锁相环在40 nm CMOS工艺下实现,在1.1 V的供电电压下,功耗为7.55 mW;在156.25 MHz频偏处,杂散为-81.66 dBc;亚采样锁相环输出时钟的相位噪声在10 kHz~100 MHz区间内积分,得到均方根抖动为0.26 ps。     

1.25～3.125 Gb/s连续数据速率CDR设计

设计了一款工作速率为1.25～3.125 Gb/s的连续可调时钟数据恢复(CDR)电路,可以满足多种通信标准的设计需求.CDR采用相位插值型双环路结构,使系统可以根据应用需求对抖动抑制和相位跟踪能力独立进行优化.针对低功耗和低噪声的需求,提出一种新型半速率采样判决电路,利用电流共享和节点电容充放电技术,数据速率为3.125 Gb/s时,仅需要消耗50 μA电流.芯片采用0.13 μm工艺流片验证,面积0.42 m㎡,功耗98 mw,测试结果表明,时钟数据恢复电路接收PRBS7序列时,误码率小于10-12.     

一种SiGe低噪声放大器测试基座的研究

对SiGe低噪声放大器(LNA)的测试技术进行了探索,开发出适合SiGe低噪声放大器的可插拔测试基座。通过对商业样品的增益G(S21)、增益平坦度、带宽、回波损耗(S11和S22)、反向隔离度(S12)1、dB压缩点(P1dB),三阶互调节点(IP3)和噪声系数(NF)等参数的测试,验证了测试系统的准确性。对所开发的单片SiGe低噪声放大器进行了测试,获得了准确的测试数据,准确表征了SiGe低噪声放大器的性能。     

一种7GHz～20GHz宽带频率综合器的设计

文章介绍了一种PLL频率合成技术获得的7GHz～20GHz的宽频带、小步进、小体积、低杂散、低相噪的频率综合器的实现方法.该方法采用Hititte公司生产的宽带VCO HMC587LC4B和鉴相器HMC702LP6C,运用锁相倍频模式,在55mm×70mm×16mm的体积内实现了7GHz～20GHz的频率输出,并且达到...     

氢气直流放电的等离子体数值模拟研究

针对低气压、弱电离条件下的氢气放电,建立了二维直流放电模型,建模中修正了有关文献中边界条件的不足,在阴极处,引入了金属电子溢出功和二次电子发射系数来表征电子与离子密度之间的关系;同时由动理论表征了电子能量的分布,依据双流体理论,以作者所分析确定的主要影响低气压、弱电离条件下氢气放电的11种碰撞反应为基础,进行了模拟计算.得出了迁移率、极间距和最小击穿电压间的对应关系,并将模拟曲线与标准的帕邢曲线进行了对比,得到了吻合的结果.     

Low Profile Integratable Inductor Fabricated Based on LTCC Technology for Microprocessor Power Delivery Applications

A novel low profile power inductor suitable for planar integration is designed and fabricated based on low temperature co-fired ceramics technology for microprocessor power delivery applications. The inductor was designed to operate at a switching frequency of 4 to 5MHz, carrying a nominal dc current of 20A with a ripple current of 8 to 10A in a 5-V to 1-V dc-dc converter. The design and fabrication procedure is discussed in this paper, followed by small signal measurement and magnetic characterization results. The inductor was implemented in a prototype converter and the large signal measurement results are presented and its performance evaluated     

Lasing characteristics of low-threshold oxide confinementInGaAs-GaAlAs vertical-cavity surface-emitting lasers

Some lasing characteristics of index-guided InGaAs-GaAlAs vertical-cavity surface-emitting lasers (VCSEL's) with a native oxide confinement structure, which produced a low threshold current of 70 μA, are presented. It was found that nonradiative recombination was reduced and the estimated surface recombination velocity was almost negligible. The oxidation process was uniform to produce low threshold devices while the oxidation rate was dependent on the doping or composition of DBR's     

Gain-clamped erbium-doped fiber-ring lasing amplifier with low noise figure by using an interleaver

A novel all-optical gain-clamped erbium-doped fiber-ring lasing amplifier (GC-EDFRLA) has been demonstrated, in which the odd port of a 100/200-G interleaver was used to form a fiber-ring cavity to produce lasing oscillation for locking the gain and its even port was employed to export the amplified signals. In such a way, the problem existing in the conventional GC-EDFRLA is solved. The signal can be exported separately without the lasing power while the noise figure (NF) is very low. Finally, the GC-EDFRLA with a low NF of 4.2 dB was achieved.