High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications

A high-speed driving scheme and a compact high-speed low-power rail-to-rail class-B buffer amplifier, which are suitable for small- and large-size liquid crystal display applications, are proposed. The driving scheme incorporates two output driving stages in which the output of the first output driving stage is connected to the inverting input and that of the second driving stage is connected to the capacitive load. A compensation resistor is connected between the two output stages for stability. The second output stage is used to improve the slew rate and the settling time. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. This increases the speed of the circuit without increasing static power consumption too much. A rail-to-rail folded-cascode differential amplifier is used to amplify the input signal difference and supply the bias voltages for the second stage. An experimental prototype output buffer implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the circuit draws only 7-/spl mu/A static current and exhibits the settling times of 2.7 /spl mu/s for rising and 2.9 /spl mu/s for falling edges for a voltage swing of 3.3 V under a 600-pF capacitance load with a power supply of 3.3 V. The active area of this buffer is only 46.5/spl times/57/spl mu/m/sup 2/.     

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers

We report an interdigitated p-i-n photodetector fabricated on a 1-/spl mu/m-thick Ge epitaxial layer grown on a Si substrate using a 10-/spl mu/m-thick graded SiGe buffer layer. A growth rate of 45 /spl Aring//s/spl sim/60 /spl Aring//s was achieved using low-energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had a threading dislocation density of 10/sup 5/ cm/sup -2/ and a rms surface roughness of 3.28 nm. The 3-dB bandwidth and the external quantum efficiency were measured on a photodetector having 1-/spl mu/m finger width and 2-/spl mu/m spacing with a 25/spl times/28 /spl mu/m/sup 2/ active area. At a wavelength of 1.3 /spl mu/m, the bandwidth was 2.2, 3.5, and 3.8 GHz at bias voltages of -1, -3, and -5 V, respectively. The dark current was 3.2 and 5.0 /spl mu/A at -3 and -5 V, respectively. This photodetector exhibited an external quantum efficiency of 49% at a wavelength of 1.3 /spl mu/m.     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-/spl mu/m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 /spl mu/s.     

AlGaN/GaN/InGaN/GaN DH-HEMTs with an InGaN notch for enhanced carrier confinement

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin In/sub x/Ga/sub 1-x/N(x=0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm/sup 2//V/spl middot/s and a sheet resistance of 420 /spl Omega//sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 14.5 GHz, and a peak power gain cutoff frequency (f/sub max/) of 45.4 GHz were achieved on a 1/spl times/100 /spl mu/m device. The off-state source-drain leakage current is as low as /spl sim/5 /spl mu/ A/mm at V/sub DS/=10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz.     

Novel self-convergent programming method using source-induced band-to-band hot electron injection

The authors describe a novel self-converging programming method using the source-induced band-to-band hot electron (SIBE) injection. This method features low current, high speed, and good reliability, and automatically converges at the desired threshold voltage state without any conventional verification operations. The programming leakage current of this method is only about 3 /spl mu/A//spl mu/m, and the programming time is as low as 30 /spl mu/s. A threshold voltage model is also proposed and shows good consistency with measured results.     

A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Fast switching bistable electromagnetic microactuator

A fast switching electromagnetic microactuator with two stable positions is presented. The actuator of size 2.0/spl times/2.2 mm is fabricated using UV-LIGA technology. Test results show that a current pulse with an amplitude of 50 mA is needed for the actuator's switching between two stable states, and the switching time is approximately 20 /spl mu/s. The displacement of the actuator is about 17 /spl mu/m.     

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.     

Metal-defined polymeric variable optical attenuator

A variable optical attenuator (VOA) based on a metal-defined polymeric optical waveguide has been demonstrated for the first time. The metal film stressor deposited on top of the upper cladding layer not only produces the refractive index change within the core layer, but also acts as a thin-film heater allowing thermal tuning of the optical power within a metal-defined optical waveguide. Fabricated devices exhibit greater than 25 dB of optical attenuation with an applied electrical current of /spl sim/40 mA at 1550-nm wavelength. The switching speed of the VOA exhibits 800 /spl mu/s of rising and 720 /spl mu/s of falling time.     

A memory-cell array with normally off-type Schottky-Barrier FET's

The potential of the metal-semiconductor field-effect transistor (MESFET) as a device for a dc-stable fixed-address memory-cell array is described. The implementation of dc-coupled circuits with `normally off' MESFET's having 1-/spl mu/m gate lengths yields several inherent advantages: high packing density, low power dissipation, low-power-delay time product, and low number of masking steps for transistors, diodes, and resistors. To demonstrate these advantages a fixed-address memory array with dc-stable cells has been chosen. The integrated cell area is 2.6 mil. For a supply voltage V/SUB s/=0.6 V, a standby power dissipation per cell of 5 /spl mu/W has been achieved. The cell switches within 4 ns. The differential sense current in the digit lines is /spl Delta/I/SUB s/=6 /spl mu/A.     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

Electrically-pumped vertical-cavity lasers with Al/sub x/O/sub y/-GaAs reflectors

We have fabricated the first electrically-pumped vertical-cavity surface-emitting lasers (VCSELs) which use oxide-based distributed Bragg reflectors (DBRs) on both sides of the gain region. They require a third the epitaxial growth time of VCSELs with semiconductor DBRs. We obtain threshold currents as low as 160 /spl mu/A in VCSELs with an active area of 8 /spl mu/m/spl times/8 /spl mu/m using a two quantum well InGaAs-GaAs active region. By etching away mirror pairs from the top reflector, quantum efficiencies as high as 61% are attained, while still maintaining a low threshold current of 290 /spl mu/A.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

Low-loss, high-voltage 6H-SiC epitaxial p-i-n diode

The p-i-n diodes were fabricated using 31 /spl mu/m thick n/sup -/- and p-type 6H-SiC epilayers grown by horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively. The diode exhibited a very high breakdown voltage of 4.2 kV with a low on-resistance of 4.6 m/spl Omega/cm/sup 2/. This on-resistance is lower (by a factor of five) than that of a Si p-i-n diode with a similar breakdown voltage. The leakage current density was substantially lower even at high temperatures. The fabricated SiC p-i-n diode showed fast switching with a turn-off time of 0.18 /spl mu/s at 300 K. The carrier lifetime was estimated to be 0.64 /spl mu/s at 300 K, and more than 5.20 /spl mu/s at 500 K. Various characteristics of SiC p-i-n diodes which have an advantage of lower power dissipation owing to conductivity modulation were investigated.     

Noise-shaping sense amplifier for MRAM cross-point arrays

A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (a counter) is presented for use with cross-point MRAM arrays and magnetic tunnel junction memory cells. The presented technique eliminates the need for precision components, the use of calibrations, and reduces the effects of power supply noise. To obviate the effects of cell-to-cell variations in the array, a digital self-referencing scheme using the counter is presented. Measured experimental results in a 180-nm CMOS process indicate an RMS sensing noise of 20 /spl mu/V for a 5-/spl mu/s sense time. Further increases in sense time are shown to increase the signal-to-noise ratio. The current used by the sense amplifier and counter was measured as 10 /spl mu/A when running at 100 MHz or 10 mA when 1000 sense amplifiers are used with a memory subarray having 1000 bitlines.