The effect of ionization and displacement damage on minority carrier lifetime

Based on 1 MeV electrons and 40 MeV Si ion irradiations, the contribution of ionization and displacement damage to the decrease in the minority carrier lifetime of gate controlled lateral PNP (GLPNP) transistors is investigated by gate sweeping (GS) technique. Molecular hydrogen is employed to increase the ionization radiation sensitivity and help to understand the relationship between the minority carrier lifetime and ionization damage. Experimental results show that 1 MeV electrons mainly induce ionization damage to GLPNP transistors, 40 MeV Si ions primarily produce displacement defects in silicon bulk. For 40 MeV Si ions, with increasing the irradiation dose, the densities of interface trap and oxide charge are almost no change, the minority carrier lifetime obviously decreases. The decrease of the minority carrier lifetime is due to bulk traps induce by 40 MeV Si ions. For 1 MeV electrons, with increasing the irradiation dose, the densities of interface trap and oxide charge for the GLPNP with and without soaked in H₂ increase, and the minority carrier lifetime decreases. Compared with the GLPNP transistors without soaking in H₂, the density of the interface traps the irradiated GLPNP transistors by 1 MeV electrons and soaked in H₂ are larger and the minority carrier lifetime is lower. Therefore, both ionization and displacement damage can induce the decreases in the minority carrier lifetime including bulk minority carrier lifetime and surface minority carrier lifetime.     

Effect of minority carrier trapping on the low-temperature characteristics of Si transistors

The effect of minority carrier traps on certain transistor characteristics is calculated. It is shown that trapping of electrons by donors in the base region of Si transistors can lead to the degradation with increasing temperature in β and fTof the type observed by Schlig on n-p-n Si transistors.     

High-current-gain submicrometer InGaAs/InP heterostructure bipolartransistors

Common-emitter current gains of 115 and 170 are achieved in transistors with emitter dimensions as small as 0.3×3 and 0.8×3 μm², respectively. These results are comparable with scaling experiments reported for Si bipolar devices and represent a significant improvement over AlGaAs/GaAs heterostructure bipolar transistors. Both the low surface recombination velocity and nonequilibrium carrier transport in the thin (800-Å) InGaAs base enhance the DC performance of these transistors     

Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

Silicon-based semiconductor heterostructures: column IV bandgapengineering

The use of strained layer epitaxy to grow high-quality Ge_x Si_1-x/Si heterostructures and their application to a wide range of heterostructure devices are addressed. The author reviews the mechanisms of strained layer growth, the bandstructure of the resulting material, and its use in test devices, including superlattice avalanche photodiodes for fiber optic communication, intrasubband optical detectors and arrays operating in the 10-15 μm wavelength range, mobility enhanced modulation-doped transistors, heterojunction bipolar transistors with cutoff frequencies of 75 GHz, and negative resistance devices based on resonant tunneling and real-space carrier transfer     

In situ-doped amorphous Si0.8C0.2 emitterbipolar transistors

The fabrication and characterization of in situ-doped amorphous Si _0.8C_0.2 emitter transistors are presented. Emitter Gummel numbers exceeding 10¹⁴ s/cm⁴ are reported for the first time in this type of structure. The high values obtained for G_E are believed to be due to the valance band discontinuity between the Si_0.8C_0.2 layer and the crystalline part of the emitter, which effectively blocks the minority carrier injection from the base into the noncrystalline part of the emitter     

基区复合电流对双极晶体管厄利电压的影响

推导了在考虑了基区复合电流后双极晶体管厄利电压的理论表达式。用该表达式计算了 Si/Si Ge异质结双极晶体管的厄利电压 ,并且与仿真结果进行了比较。比较结果表明 ,两种情况下计算出的厄利电压值符合良好     

THE EFFECT OF DOPANT OUTDIFFUSION ON THE NEUTRAL BASE RECOMBINATION CURRENT IN Si/SiGe/Si HETEROJUNCTION BIPOLAR TRANSISTORS

A new analytical model for the base current of Si/SiGe/Si heterojunction bipolar transistors(HBTs) has been developed. This model includes the hole injection current from the base to the emitter, and the recombination components in the space charge region(SCR) and the neutral base. Distinctly different from other models, this model includes the following effects on each base current component by using the boundary condition of the excess minority carrier concentration at SCR boundaries: the first is the effect of the parasitic potential barrier which is formed at the Si/SiGe collector-base heterojunction due to the dopant outdlffusion from the SiGe base to the adjacent Si collector, and the second is the Ge composition grading effect. The effectiveness of this model is confirmed by comparing the calculated result with the measured plot of the base current vs. the collector-base bias voltage for the ungraded HBT. The decreasing base current with the increasing the collector-base reverse bias voltage is successfully explained by this model without assuming the short-lifetime region close to the SiGe/Si collector-base junction, where a complete absence of dislocations is confirmed by transmission electron microscopy (TEM)[1]. The recombination component in the neutral base region is shown to dominate other components even for HBTs with a thin base, due to the increased carrier storage in the vicinity of the parasitic potential barrier at collector-base heterojunction.     

On the profile design and optimization of epitaxial Si- andSiGe-base bipolar technology for 77 K applications. I. Transistor DCdesign considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

Si/GexSi1-x heterojunction bipolartransistors with the GexSi1-x base formed by Geion implantation in Si

We have fabricated n-p-n, Si/Ge₂Si_1-x heterojunction bipolar transistors (HBTs) with the Ge_xSi_1-x base formed by high-dose Ge implantation followed by solid phase epitaxy. The fabrication technology is a standard self-aligned, double polysilicon process scheme for Si with the addition of the high-dose Ge implantation. The transistors are characterized by a 60 mn-wide neutral base with a Ge concentration peak of ≈8 at.% at the base-collector junction. The HBTs show good electrical characteristics and compared to Si homojunction transistors show lower base resistance, larger values of current gain, and a lower emitter-to-collector transit time     

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—DC Analysis and Modeling Toward Optimum Transistor Structure

Scaling of silicon technology continues while a research has started in other novel materials for future technology generations beyond year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. The authors investigated different CNT-based field effect transistors (CNFETs) for an optimal switch. Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. The authors have performed a dc analysis and determined how noise margin and voltage swing vary as a function of tube diameter and power-supply voltage. The dc analysis of single-tube SB CNFET transistors revealed that the optimum CNT diameter for achieving the best I_ON-to-I_OFF ratio while maintaining a good noise margin is about 1 to 1.5 nm. Despite several serious technological barriers and challenges, CNTs show a potential for future high-performance devices as they are being researched     

Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolartransistors

In this work a comprehensive investigation of low-frequency noise in ultrahigh vacuum/chemical vapor deposition (UHV/CVD) Si and SiGe bipolar transistors is presented. The magnitude of the noise of SiGe transistors is found to be comparable to the Si devices for the identical profile, geometry, and bias. A comparison with different technologies demonstrates that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs heterojunction bipolar transistors (HBT's) and conventional Si bipolar junction transistors (BJT's). Results from different bias configurations show that the 1/f base noise source is dominant in these devices. The combination of a 1/Area dependence on geometry and near quadratic dependence on base current indicates that the 1/f noise sources are homogeneously distributed over the entire emitter area and are probably located at the polysilicon-Si interface. Generation/recombination (Gm) noise and random telegraph signal (RTS) noise was observed in selected Si and SiGe devices. The bias dependence and temperature measurements suggest that these G/R centers are located in the base-emitter space charge region. The activation energies of the G/R traps participating in these noise processes were found to be within 250 meV of the conduction and valence band edges     

Band-gap narrowing and high-frequency characteristics ofSi/GexSi1-x heterojunction bipolar transistorsformed by Ge ion implantation in Si

Si/Ge_xSi_1-x heterojunction n-p-n bipolar transistors (HBT's) with a double-polysilicon self-aligned structure were fabricated by using high dose Ge implantation for the formation of the Si/Ge_xSi_1-x heterostructure and As and BF₂ implantation for emitter and base doping. DC and high frequency electrical characteristics are investigated for Ge concentrations up to 7 at.% and for base widths down to 35 nm. Improvements in electrical characteristics compared to reference Si transistors are demonstrated. Experimental data indicating that these improvements are related to an effective band gap engineering are shown and discussed     

Si／Si1—xGex异质结器件

本文综述了国外Si/Si_(1-x)Ge_xHBT的发展状况,把出Si_(1-x)Ge_xHBT的特点和优越性,分析了Si_(1-x)Ge_xHBT的制造技术和设备要求,指出了Si/Si_(1-x)Gex器件的应用前景。     

Seamless On-Wafer Integration of Si(100) MOSFETs and GaN HEMTs

The first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated. To enable a fully Si-compatible process, we fabricated a novel Si(100)-GaN-Si(100) virtual substrate through a wafer bonding and etch-back technique. The high thermal stability of nitride semiconductors allowed the fabrication of Si MOSFETs on this substrate without degrading the performance of the GaN epilayers. After the Si devices were fabricated, the nitride epilayer is exposed, and the nitride transistors are processed. By using this technology, GaN and Si devices separated by less than 5 mum from each other have been fabricated, which is suitable for building future heterogeneous integrated circuits.     

石墨烯/Si晶体管的研究进展

石墨烯具有很多优异的力学、电学和结构特性,可用于制备高速、低功耗的半导体电子器件和集成电路芯片。简要介绍了三种石墨烯/Si的制备方法,即剥离法、外延法、剪切和选择转移印刷法,其中外延生长的石墨烯被认为是最终实现碳集成电路的唯一途径。并给出了采用上述方法制备的石墨烯/Si晶体管的电阻、磁阻、载流子迁移和输运特性以及量子霍尔效应(QHE)等电学特性。发现石墨烯/Si晶体管最高频率达155GHz,在室温下具有异常的量子霍尔效应和分数量子霍尔效应。其电荷载流子浓度在电子和空穴之间连续变化,可高达1013 cm-2,迁移率可达2×105 cm2/(V.s)。     

Effect of band alignment and density of states on the collector current in p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs

p-Si/n-Si/sub 1-y/C/sub y//p-Si heterojunction bipolar transistors with varying carbon fractions in the base were grown by rapid thermal chemical vapor deposition (RTCVD), to better understand the potential of Si/sub 1-y/C/sub y/ in enhancing the performance of Si-based bipolar technology. The band line-up issues which make Si/sub 1-y/C/sub y/ a desirable choice for forming the base region in a p-n-p HBT are discussed. Electrical measurements performed on the p-Si/n-Si/sub 1-y/C/sub y//p-Si HBTs (y=0.6, 0.8 at.%) are used to extract important information regarding the electronic properties of the Si/Si/sub 1-y/C/sub y/ material system, e.g., the bandgap reduction in Si/sub 1-y/C/sub y/ compared to Si and minority carrier recombination lifetime in Si/sub 1-y/C/sub y/. Temperature dependent measurements of the collector current were performed to extract the bandgap narrowing at the Si/Si/sub 1-y/C/sub y/ heterojunction. This paper includes a detailed analysis of the impact of heavy doping and reduced density of states in Si/sub 1-y/C/sub y/ compared to Si on the extraction of the energy bandgap offset, and on the collector current of p-n-p HBTs. The impact of the reduced density of states on the design of p-n-p Si/Si/sub 1-y/C/sub y/ HBTs is discussed. The measured value of the energy band offset is (65 meV/at.% C) very close to previously measured values of the conduction band offset at the Si/Si/sub 1-y/C/sub y/ heterojunction. The results are thus consistent with a band line-up at the Si/Si/sub 1-y/C/sub y/ interface that is dominated by a conduction band offset with little if any valence band offset.     

Characteristics of p- and n-channelpoly-Si/Si1-xGex/Si sandwiched conductivitymodulated thin-film transistors

Both p- and n-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistors (CMTFTs) are demonstrated and experimentally characterized. The transistors use a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide a high on-state current. Results show that the transistors provide a high on-state current as well as a low leakage current compared to those of conventional offset drain TFTs. The p- and n-channel CMTFTs can be combined to form CMOS drivers, which are very suitable for use in low temperature large area electronic systems on glass applications