Parallel fuzzy inference with an optoelectronic H-tree architecture

Fuzzy inference is a method of reasoning with imprecise information. The mathematical operations of fuzzy inference can be stated in terms of generalized vector algebra, in which multiplication and summation are generalized to min and max operations. An optoelectronic H-tree architecture is ideally suited to perform these generalized vector operations in parallel and requires only a simple imaging optical interconnection. Appropriate data encodings and electronic circuitry permit large scale, pipelined systems.     

Time multiplexing and control for optical cellular-hypercube arrays

We discuss the cellular-hypercube optical free-space interconnection architecture and its implementation by two-dimensional smart-pixel optoelectronic cellular arrays. We emphasize the behavior of the cellular hypercube in performing shift-invariant parallel shifts of data, a basic requirement of most single-instruction multiple-data algorithms. We present a time-multiplexing scheme for realizing the cellular hypercube, showing that the communication time is inversely proportional to the number of optical detectors per cell. We also present an improved hybrid interconnection network with improved performance that combines the cellular hypercube and mesh, using optics for the longer-distance connections and electronics for nearest-neighbor connections.     

Optical content-addressable parallel processor for high-speed database processing

We extend the concept of optical content-addressable parallel processing [Appl. Opt. 31, 3241 (1992)] to a novel architecture designed specifically for the parallel and high-speed implementation of database operations called optical content-addressable parallel processor for relational database processing (OCAPPRP). An OCAPPRP combines a parallel model of computation, associative processing, with parallel and high-speed technology optics. The architecture is developed to provide optimal support for high-speed parallel equivalence (pattern matching) and relative-magnitude searches (greater than and lesser than). Distinctive features of the proposed architecture include (1) a two-dimensional match-compare unit for two-dimensional pattern matching, (2) constant-time retrieval of database entries, (3) an optical word and bit-parallel relative-magnitude single-step algorithm, and (4) the capability of constanttime sorting. Since relational database operations rely heavily on parallel equivalence or relativemagnitue searches, database processing is an excellent candidate for implementation on an OCAPPRP. The architecture delivers a speedup factor of n over conventional optical database architectures, where n is the number of rows in a database table. We present an overview of the architecture followed by its optical implementation. The representative relational database operations, intersection, and selection are outlined to illustrate the architecture's potential for efficiently supporting high-speed database processing.     

Optoelectronic parallel-matching architecture: architecture description, performance estimation, and prototype demonstration

We propose an optoelectronic parallel-matching architecture (PMA) that provides powerful processing capabilities in global processing compared with conventional parallel-computing architectures. The PMA is composed of a global processor called a parallel-matching (PM) module and multiple processing elements (PE's). The PM module is implemented by a large-fan-out free-space optical interconnection and a PM smart-pixel array (PM-SPA). In the proposed architecture, by means of the PM module each PE can monitor the other PE's by use of several kinds of global data matching as well as interprocessor communication. Theoretical evaluation of the performance shows that the proposed PMA provides tremendous improvement in global processing. A prototype demonstrator of the PM module is constructed on the basis of state-of-the-art optoelectronic devices and a diffractive optical element. The prototype is assumed for use in a multiple-processor system composed of 4 x 4 PE's that are completely connected through bit-serial optical communication channels. The PM-SPA is emulated by a complex programmable device and a complementary metal-oxide semiconductor photodetector array. On the prototype demonstrator the fundamental operations of the PM module were verified at 15 MHz.     

Digital Fourier optics

Analog Fourier optical processing systems can perform important classes of signal processing operations in parallel, but suffer from limited accuracy. Digital-optical equivalents of such systems could be built that share many features of the analog systems while allowing greater accuracy. We show that the digital equivalent of any system consisting of an arbitrary number of lenses, niters, spatial light modulators, and sections of free space can be constructed. There are many possible applications for such systems as well as many alternative technologies for constructing them; this paper stresses the potential of free-space interconnected active-device-plane-based optoelectronic architectures as a digital signal processing environment. Implementation of the active-device planes through hybridization of optoelectronic components with silicon electronics should allow the realization of systems whose performance exceeds that of purely electronic systems.     

Node-based reconfigurable volume interconnections. 1. Principles and optical design

We present a general-purpose three-dimensional interconnection network that models various parallel operations between two data planes. This volume interconnection system exhibits reconfigurable capabilities because of parallel and externally weighted interconnection modules, called nodes. We propose a generic optical implementation based on the cascading of two planar hologram arrays, coupled with a bistable optically addressed spatial light modulator. The role of this component is discussed in terms of energy regeneration and spatial cross-talk limitation. As an example, a binary matrix-matrix multiplier is implemented that uses a ferroelectric liquid-crystal light valve.     

Optical binary de Bruijn networks for massively parallel computing: design methodology and feasibility study

The interconnection network structure can be the deciding and limiting factor in the cost and the performance of parallel computers. One of the most popular point-to-point interconnection networks for parallel computers today is the hypercube. The regularity, logarithmic diameter, symmetry, high connectivity, fault tolerance, simple routing, and reconfigurability (easy embedding of other network topologies) of the hypercube make it a very attractive choice for parallel computers. Unfortunately the hypercube possesses a major drawback, which is the complexity of its node structure: the number of links per node increases as the network grows in size. As an alternative to the hypercube, the binary de Bruijn (BdB) network has recently received much attention. The BdB not only provides a logarithmic diameter, fault tolerance, and simple routing but also requires fewer links than the hypercube for the same network size. Additionally, a major advantage of the BdB network is a constant node degree: the number of edges per node is independent of the network size. This makes it very desirable for large-scale parallel systems. However, because of its asymmetrical nature and global connectivity, it poses a major challenge for VLSI technology. Optics, owing to its three-dimensional and globalconnectivity nature, seems to be very suitable for implementing BdB networks. We present an implementation methodology for optical BdB networks. The distinctive feature of the proposed implementation methodology is partitionability of the network into a few primitive operations that can be implemented efficiently. We further show feasibility of the presented design methodology by proposing an optical implementation of the BdB network.     

Parallel RSA encryption based on tree architecture

Parallelism is a technique to accelerate various applications. Nowadays, parallel operations are used to solve computer problems such as sort, search, and cryptography, which result in a reasonable speed. Sequential algorithms can be parallelized by being implemented on parallel architectures. Cryptography is the science of hiding information, which by the increase in the applications on insecure communication environments, has become one of the most important aspects of the digital world. In this article, we propose a parallel RSA utilizing parallel processing on RSA using tree architecture. RSA is a well-known public key cryptography which is not as fast as symmetric cryptographies. Parallelizing it, we can achieve speedup and more security. We also investigate the state of the art methods of RSA and figure out that their low speed can be faster with reasonable security using parallel architecture.     

Optical finite impulse response neural networks

The finite impulse response neural network is described in detail. Different algorithms capable of temporal back-propagation are considered, including a novel modification to the conventional algorithm, called the delayed-feedback back-propagation algorithm. We present and analyze different optoelectronic processors making use of adaptive volume holograms and three-dimensional optical processing. Two single-layer architectures are presented: the input delay plane architecture and the output delay plane architecture. By combining them it is possible to implement both forward and backward propagation in two multi-layer architectures: the first making use of the conventional temporal back-propagation and the second making use of delayed-feedback back-propagation.     

Modified engagement method for matrix operation

We describe a modified engagement method for matrix operation based on a two-dimensional crossed-ring interconnection network. Our method incorporates fewer steps than that reported by Bocker et al. [Appl. Opt. 22, 804 (1983)], and its performance is found to be the most efficient (minimum steps) in comparison with other systolic and/or engagement methods for matrix operation. Thus, it may be helpful for other optical and electronic implementations of matrix operations. One compact optoelectronic integrity approach for implementing the modified engagement method is briefly described.     

Standard cell-based implementation of a digital optoelectronic neural-network hardware

A standard cell-based implementation of a digital optoelectronic neural-network architecture is presented. The overall structure of the multilayer perceptron network that was used, the optoelectronic interconnection system between the layers, and all components required in each layer are defined. The design process from VHDL-based modeling from synthesis and partly automatic placing and routing to the final editing of one layer of the circuit of the multilayer perceptrons are described. A suitable approach for the standard cell-based design of optoelectronic systems is presented, and shortcomings of the design tool that was used are pointed out. The layout for the microelectronic circuit of one layer in a multilayer perceptron neural network with a performance potential 1 magnitude higher than neural networks that are purely electronic based has been successfully designed.     

Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor

Addition is the most primitive arithmetic operation in digital computation. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logic operations. With the binary number system, addition speed is inevitably limited by the carry-propagation schemes. On the other hand, carry-free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to handle the parallel MSD addition and subtraction operations. An optoelectronic shared content-addressable memroy is introduced. The shared content-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electronics to postprocess and derive logic decisions. We analyze the accuracy that the required optical hardware can deliver by using a statistical cross-talk-rate model that we propose. We also evaluate other important device and system performanceparameters, such as the memory capacity or the maximum number of parallel bits the adder can handle in terms of a given cross-talk rate at a certain repetition rate, the corresponding diffraction-limited memory density, and the system's power efficiency. To confirm the underlining operational principles of the proposed optoelectronic shared content-addressable-memory MSD adder, we design and perform initial experiments for handling 8-bit MSD number addition and subtraction and present the results.     

Three-dimensional optoelectronic stacked processor by use of free-space optical interconnection and three-dimensional VLSI chip stacks

We present a demonstration system under the three-dimensional (3D) optoelectronic stacked processor consortium. The processor combines the advantages of optics in global, high-density, high-speed parallel interconnections with the density and computational power of 3D chip stacks. In particular, a compact and scalable optoelectronic switching system with a high bandwidth is designed. The system consists of three silicon chip stacks, each integrated with a single vertical-cavity-surface-emitting-laser-metal-semiconductor-metal detector array and an optical interconnection module. Any input signal at one end stack can be switched through the central crossbar stack to any output channel on the opposite end stack. The crossbar bandwidth is designed to be 256 Gb/s. For the free-space optical interconnection, a novel folded hybrid micro-macro optical system with a concave reflection mirror has been designed. The optics module can provide a high resolution, a large field of view, a high link efficiency, and low optical cross talk. It is also symmetric and modular. Off-the-shelf macro-optical components are used. The concave reflection mirror can significantly improve the image quality and tolerate a large misalignment of the optical components, and it can also compensate for the lateral shift of the chip stacks. Scaling of the macrolens can be used to adjust the interconnection length between the chip stacks or make the system more compact. The components are easy to align, and only passive alignment is required. Optics and electronics are separated until the final assembly step, and the optomechanic module can be removed and replaced. By use of 3D chip stacks, commercially available optical components, and simple passive packaging techniques, it is possible to achieve a high-performance optoelectronic switching system.     

Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing

A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.     

Impact of gate fan-in and fan-out limits on optoelectronic digital circuits

The impact of gate fan-in and fan-out limits on digital circuit delay is discussed with a set of benchmark circuits. This research presents the advantages of exploiting the ability of optoelectronic gates to perform both logic operations and optical interconnections with systematic optimization. It is possible for gate-level optical interconnected optoelectronic circuits to compete with their pure silicon counterparts in terms of the combinational circuit delay and system clock rate.     

Simulating free-space optical computing architectures

Major issues in optoelectronic system design include timing, synchronization, and control. Designing free-space optical computing architectures is difficult because of the high degree of system complexity, parallelism, and concurrency in conjunction with the high cost and lack of availability of devices. Current simulation tools lack the expressiveness to model the system structure and behavior of parallel and concurrent architectures, thus making them inefficient and ineffective. We show that Petri nets, compared with other system-modeling methodologies, are more efficient and effective at expressing the functional, behavioral, and structural properties of parallel and concurrent architectures. We show how an extended version of the standard Petri net, a timed-colored Petri net, is used to model and simulate free-space optoelectronic computing architectures. We also present methods for analysis of system timing, synchronization, and control behavior.     

Demonstration of a multichannel optical interconnection by use of imaging fiber bundles butt coupled to optoelectronic circuits

Through five experiments, we demonstrate and characterize the basic functionality of imaging fiber bundles for optoelectronic chip-level interconnections. We demonstrate the transmission of spot arrays with spot sizes and a spot pitch roughly equal to 2 and 4 times the core pitch, respectively. We show that optoelectronic integrated circuits, including sources and detectors, can be butt coupled directly to fiber bundles without any additional optical elements. We demonstrate a 16-channel interconnect with -23 dB of cross talk, and we characterize the most significant optical loss mechanism. Finally, we show how imaging fiber bundles can be used to implement more complex interconnection structures by an example of a hybrid-bonded structure that implements a low-cost, high-connectivity solution for more advanced system architectures.     

Performance scaling comparison for free-space optical and electrical interconnection approaches

Projected performance metrics of free-space optical and electrical interconnections are estimated and compared in terms of smart-pixel input-output bandwidth density and practical geometric packaging constraints. The results suggest that three-dimensional optical interconnects based on smart pixels provide the highest volume, latency, and power-consumption benefits for applications in which globally interconnected networks are required to implement links across many integrated-circuit chips. It is further shown that interconnection approaches based on macro-optical elements achieve better scaling than those based on micro-optical elements. The scaling limits of micro-optical-based architectures stem from the need for repeaters to overcome diffraction losses in multichip architectures with high bisection bandwidth. The overall results provide guidance in determining whether and how strongly a free-space optical interconnection approach can be applied to a given multiprocessor problem.     

Sliding-banyan network performance analysis

The sliding-banyan (SB) network employs an interleaved multistage shuffle-exchange topology, implemented with a three-dimensional free-space interconnection architecture that connects a multichip backplane to itself. Surface-normal emitters and detectors, which compose the stages' input-output, are spatially multiplexed within the same chip location, along with electronic control and switching resources. A simple deflection self-routing scheme minimizes internal contention, providing efficient use of switching and interconnection resources. The blocking performance of the SB is quantified through simulations based on realistic nonuniform traffic patterns. Results show that the SB architecture requires significantly fewer resources than other self-routing banyan-based networks. The multistage-switching and interconnection-resource requirements are close to the theoretical minimum for nonblocking networks, and the SB's distributed self-routing control resources grow only approximately linearly with the number of nodes, providing good scalability.