Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors

Using InP-InGaAs heterojunction bipolar transistor (HBT) technology, we have successfully designed and fabricated a low-power 1:16 demultiplexer (DEMUX) integrated circuit (IC) and one-chip clock and data recovery (CDR) with a 1:4 DEMUX IC for 10-Gb/s optical communications systems. The InP-InGaAs HBTs were fabricated by a nonself-aligned process for high uniformity of device characteristics and producibility. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consist of approximately 1200 and 460 transistors, respectively. We have confirmed error-free operation at 10 Gb/s for all data outputs of both ICs. The 1:16 DEMUX IC and the one-chip CDR with the 1:4 DEMUX IC consume only 1 W and 950 mW, respectively. These results demonstrate the feasibility of InP-InGaAs HBTs for low power high-integration optical communication ICs.     

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f/sub T/ and f/sub max/ of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.     

A novel InGaP/Al/sub x/Ga/sub 1-x/As/GaAs CEHBT

A new and interesting InGaP/Al/sub x/Ga/sub 1-x/As/GaAs composite-emitter heterojunction bipolar transistor (CEHBT) is fabricated and studied. Based on the insertion of a compositionally linear graded Al/sub x/Ga/sub 1-x/As layer, a near-continuous conduction band structure between the InGaP emitter and the GaAs base is developed. Simulation results reveal that a potential spike at the emitter/base heterointerface is completely eliminated. Experimental results show that the CEHBT exhibits good dc performances with dc current gain of 280 and greater than unity at collector current densities of J/sub C/=21kA/cm/sup 2/ and 2.70/spl times/10/sup -5/ A/cm/sup 2/, respectively. A small collector/emitter offset voltage /spl Delta/V/sub CE/ of 80 meV is also obtained. The studied CEHBT exhibits transistor action under an extremely low collector current density (2.7/spl times/10/sup -5/ A/cm/sup 2/) and useful current gains over nine decades of magnitude of collector current density. In microwave characteristics, the unity current gain cutoff frequency f/sub T/=43.2GHz and the maximum oscillation frequency f/sub max/=35.1GHz are achieved for a 3/spl times/20 /spl mu/m/sup 2/ device. Consequently, the studied device shows promise for low supply voltage and low-power circuit applications.     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

High-performance InGaP/GaAs HBTs with compositionally graded bases grown by solid-source MBE

N-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with compositionally graded In/sub x/Ga/sub 1-x/As (Be doped) bases have been successfully grown by solid-source molecular beam Epitaxy (SSMBE) using a gallium phosphide (GaP) decomposition source. In this paper, the dc and RF characteristics of HBTs with different indium mole fractions in the graded In/sub x/Ga/sub 1-x/As base (x:0 /spl rarr/ ;0.1 and x:0 /spl rarr/ 0.05) are measured to investigate optimum-grading profiles. The measured average current gains, /spl beta/s of a control sample, a 10% graded-base sample and a 5% graded-base sample, are 162, 397 and 362, respectively. To our knowledge, these current gains are the highest values ever reported in compositionally graded-base InGaP/GaAs HBTs with a base sheet resistance R/sub sh/ of /spl sim/200 /spl Omega//sq establishing a new benchmark for InGaP/GaAs HBTs. Furthermore, these compositionally graded-base HBTs show higher unity current/gain cutoff frequency, f/sub T/ and maximum oscillation frequency, f/sub max/. Compared to the control sample with the same base thickness, the base transit time /spl tau//sub B/ of the graded sample is reduced by /spl sim/15% to /spl sim/20% by the induced built-in potential, resulting in an increase of f/sub max/ from 16 to 18.5 GHz in a device with an emitter size of 10/spl times/10 /spl mu/m/sup 2/. Additionally, for the 5% graded-base sample, with a 5/spl times/5 /spl mu/m/sup 2/ emitter region, f/sub T/ and f/sub max/ are 16.3 and 33.8 GHz, respectively, under low-level collector current. These results demonstrate that InGaP/GaAs HBTs with In/sub x/Ga/sub 1-x/As graded-base layers (x:0 /spl rarr/ 0.05) have the potential for high-speed analogue to digital converters.     

Ultra high-speed InP-InGaAs SHBTs with f/sub max/ of 478 GHz

InP-based single heterojunction bipolar transistors (SHBTs) for high-speed circuit applications were developed. Typical common emitter DC current gain (/spl beta/) and BV/sub CEO/ were about 17 and 10 V, respectively. Maximum extrapolated f/sub max/ of 478 GHz with f/sub T/ of 154 GHz was achieved for 0.5 /spl times/ 10 /spl mu/m/sup 2/ emitter size devices at 300 kA/cm/sup 2/ collector current density and 1.5 V collector bias. This is the highest f/sub max/ ever reported for any nontransferred substrate HBTs, as far as the authors know. This paper highlights the optimized conventional process, and the authors have great hopes for the process that offers inherent advantages for the direct implementation to high-speed electronic circuit fabrication.     

High-performance carbon-doped base GaAs/AlGaAs heterojunction bipolar transistor grown by MOCVD

High-performance HBTs with a carbon-doped base layer (p=4*10/sup 19/ cm/sup -3/) are reported. The use of carbon as a p-type dopant allows the emitter-base p-n junction to be accurately positioned relative to the heterojunction, and the MOCVD growth method ensures consistency and uniformity of the wafer epitaxial structure. Microwave HBTs with current gains h/sub FE/=50 and f/sub T/ and f/sub max/ values of 42 GHz and 117 GHz, respectively, are reported.<>     

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.     

InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f/sub /spl tau// and 505-GHz f/sub max/

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f/sub /spl tau// and 505-GHz f/sub max/, which is the highest f/sub /spl tau// reported for an InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance C/sub cb/. In addition, the base sheet resistance /spl rho//sub s/ along with the base and emitter contact resistivities /spl rho//sub c/ have been lowered. The dc current gain /spl beta/ is /spl ap/36 and V/sub BR,CEO/=5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f/sub clk/=3 to 142.0 GHz while dissipating /spl ap/800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz.     

Transistor and circuit design for 100-200-GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.     

Over 300 GHz f/sub T/ and f/sub max/ InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base

Describes 150-nm-thick collector InP-based double heterojunction bipolar transistors with two types of thin pseudomorphic bases for achieving high f/sub T/ and f/sub max/. The collector current blocking is suppressed by the compositionally step-graded collector structure even at J/sub C/ of over 1000 kA/cm/sup 2/ with practical breakdown characteristics. An HBT with a 20-nm-thick base achieves a record f/sub T/ of 351 GHz at high J/sub C/ of 667 kA/cm/sup 2/, and a 30-nm-base HBT achieves a high value of 329 GHz for both f/sub T/ and f/sub max/. An equivalent circuit analysis suggests that the extremely small carrier-transit-delay contributes to the ultrahigh f/sub T/.     

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.     

High-speed small-scale InGaP/GaAs HBT technology and itsapplication to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO₂ in the extrinsic collector. The base-collector capacitance C_BC was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO ₂, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO₂ region by 50% compared to our previous devices. The cutoff frequency f_T of 156 GHz and the maximum oscillation frequency f_max of 255 GHz were obtained at a collector current I_C of 3.5 mA for the HBT with an emitter size S_E of 0.5×4.5 μm², and f_T of 114 GHz and f_max of 230 GHz were obtained at I_C of 0.9 mA for the HBT with S_E of 0.25×1.5 μm². We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications     

Millimetre wave performance of carbon-doped-base AlGaAs/GaAs HBTs

AlGaAs/GaAs HBTs with f/sub T/ of 52 GHz and f/sub max/ of 85 GHz have been obtained using a heavily-carbon-doped base layer. The HBT epitaxial layers were prepared by low-pressure MOVPE using carbon tetrachloride as the carbon source. To the author's knowledge, this work reports the first carbon-doped AlGaAs/GaAs HBTs with f/sub T/ and f/sub max/ greater than 50 GHz.<>