50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer

A 10-GHz clock recovery from a 16×10-Gbit/s optical time-division-multiplexed (OTDM) data stream is experimentally demonstrated using an electro-absorption modulator and 40-Gbit/s electric time-division-multiplexed (ETDM) demultiplexer. The recovered clock signal exhibits excellent stability, with root square (RMS) jitter of 328 and 345 fs corresponding to back-to-back and transmission over 100 km, respectively.     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONETSTS-192 system

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-Ω on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-μm WN_x-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230°     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)     

6Gbit/s multiplexer and regenerating demultiplexer ICs for optical transmission systems based on a standard bipolar technology

Time-division 4:1 multiplexing and 1:4 demultiplexing as well as signal regeneration are important functions in high-speed optical fibre transmission systems. It has been shown by experiments that these tasks can be solved up to about 6Gbit/s by using monolithic integrated circuits fabricated with a 2 ?m standard bipolar technology.     

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.     

Toward High-Speed 40-Gbit/s Transponders

Today a 40-Gbit/s data rate is agreed by major optical telecommunication players as the next step in the network evolution, with an actual deployment foreseen in the 2007-2008 timeframe. R&D activities on technologies for 40-Gbit/s products are currently active but the path to 40-Gbit/s transponders is not yet fully settled. In this paper, we review the different component technologies currently considered for the actual development and the implementation of future 40-Gbit/s transponders. Dedicated paragraphs are devoted to electronic ICs and electrooptical devices, along with considerations on the technical solutions ensuring suitable interconnections or integration of the different components. Such advanced transponders should be compliant with the requirements of the different segments of the optical transport market. Solutions derived from choices made at lower data rates are projected for the shortest transmission paths, based on conventional nonreturn to zero modulation. In the peculiar case of long-haul transmission, signal distortion resulting from fiber propagation impairments calls for the generation of alternative modulation formats at the transmitter side and the potential need for electronic processing at the receiver side. This obviously has a clear impact on both the transponder design and the individual components features. Finally, recent advances in the field of innovative "all-optical" transponders implementing optical regeneration are also reported.     

2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs     

Differential precoder IC modules for 20-and 40-Gbit/s opticalduobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-μm gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1×10^-9     

Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.     

20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver

Using our 0.2-μm AlGaAs-GaAs-AlGaAs quantum well high electron mobility transistor (HEMT) technology, we have developed a chip set for 20-40 Gb/s fiber-optical digital transmission systems. In this paper we describe five receiver chips: a limiting amplifier with a differential gain of 17 dB and a 3 dB bandwidth of 29.3 GHz, a 40 Gb/s clock recovery, a data decision and a 1:4 demultiplexer, both for bit rates of more than 40 Gb/s, and a static 1:4 divider with operating frequencies up to 30 GHz. All presented chips were characterized on wafer with 50-Ω coplanar test probes     

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

Monolithic integrated 4:1 multiplexer and demultiplexer operating up to 4.8 Gbit/s

The letter describes the high-speed performance of a 4:1 time-division MSI multiplexer and demultiplexer, which are fabricated using advanced super self-aligned process technology (SST). The maximum operation speed of the multiplexer is 5.02 GHz under 576 mW power dissipation. The system, which is composed of a multiplexer and a demultiplexer, operates at up to 4.80 GHz. The demultiplexer has a power dissipation of 1148 mW. Interchannel interference is also examined.     

Optimum design of a 4-Gbit/s GaAs MESFET optical preamplifier

An analysis for determining the optimum MESFET gate width to optimize the sensitivity of a high-speed optical preamplifier is presented. A full MESFET model is employed including correlated gate and drain noise sources. The design of an optimum sensitivity monolithic shunt feedback amplifier, including stability requirements, is investigated. The results show that the optimum gate width for minimizing input equivalent noise is significantly larger than earlier simplfied predictions. A sensitivity improvement of 1.2 dB is demonstrated for a 4-Gbit/s MESFET optical amplifier, and results showing the dependence of optimum FET width on photodetector capacitance are described.     

40-Gbit/s SDH光纤通信系统前置放大器设计

基于0.35μm SiGe BiCMOS工艺,设计了共基极和共发共基两种输入结构的前置放大器.为获得更宽的电路带宽,共基极电路采用了电容峰化技术.电路仿真表明,采用这些技术使两种前置放大器的跨阻带宽都达到了28GHz以上,满足了40Gbit/s SDH光纤通信系统带宽要求.通过比较两种不同输入结构前置放大器的增益、带宽、电路稳定性以及噪声特性,提出了双极型晶体管实现高速前置放大器的设计方案.     

Packaging for a 40-channel parallel optical interconnection modulewith an over-25-Gbit/s throughput

NTT is currently working on developing a high-throughput interconnection module that is both compact and cost effective. The technology being developed is called “parallel inter-board optical interconnection technology”, or “ParaBIT”. The ParaBIT module that has been developed is the first step; it is a front-end module with 40 channels, a throughput of over 25 Gbit/s, and a transmission distance of over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays enable the same packaging structure to be used for both the transmitter and receiver. To achieve super-multichannel performance, high-density multiport bare-fiber (BF) connectors were developed for the module's optical interface. Unlike conventional optical connectors, these BF connectors do not need a ferrule or spring. This ensures physical contact with an excellent insertion loss (less than 0.1 dB per channel). A polymeric optical waveguide film with a 45° mirror for coupling to the VCSEL and photo-diode (PD) arrays by passive optical alignment was also developed. To facilitate coupling between the VCSEL/PD array chips and the waveguide, a packaging technique was developed to align and die bond the optical array chips on a substrate. This technique is called transferred multichip bonding (TMB); it can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques enabled ultra-parallel interconnections to be achieved in prototype ParaBIT modules     

A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication systems

We describe the design concept and performance of a 3-bit soft-decision IC, which opens a vista for new terabit-capacity optical communication systems by dramatically improving the capability of forward error correction (FEC). The proposed soft-decision IC is composed of five functional blocks, i.e., a soft-decider, an error filter, a 3-bit encoder, a 3:48 de-multiplexer, and a clock recovery circuit. The biggest challenge was the soft-decision block regenerating the common data using seven deciders with separate thresholds. We employed a novel SiGe BiCMOS process and a custom BGA package made from low-temperature co-fired ceramics to achieve a high sensitivity of 20 mVpp with a wide phase margin of 270/spl deg/ for 12.4-Gb/s nonreturn-to-zero (NRZ) data signals. The error filter and the 3-bit encoder, which are incorporated in the IC, prevent the degradation of the FEC performance due to signal noise or fluctuations. The 3:48 de-multiplexer provides an accessible interface with the FEC encoder/decoder LSI. The clock recovery circuit, based on a phase-locked-loop technology, fulfilled the jitter tolerance requirements corresponding to ITU-T G.825, even for 55% duty cycle optical return-to-zero (RZ) signals. The 3-bit soft-decision IC, in cooperation with a block turbo encoder/decoder, achieved a record net coding gain of 10.1 dB with 24.6% redundancy, which is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel.