Analytical modeling of MOSFETs channel noise and noise parameters

Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes /spl sim/5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.     

Self-heating of submicrometer InP-InGaAs DHBTs

We studied the thermal properties of submicron InP-InGaAs-InP double heterojunction bipolar transistors (DHBTs) with emitter dimensions of A = 0.25 /spl times/ 4 /spl mu/m/sup 2/. From the temperature dependence of V/sub bc/, we measured a thermal resistance of R/sub th/ = 3.3 /spl deg/C/mW for DHBTs with ion-implanted n+-InP subcollector at room temperature, compared to a high R/sub th/ = 7.5 /spl deg/C/mW from DHBTs with conventional grown InGaAs subcollector. Two-dimensional device simulations confirm the measured results.     

InGaAs-InP metamorphic DHBTs grown on GaAs with lattice-matched device performance and f/sub /spl tau//, f/sub max/>268 GHz

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on a GaAs substrate using a metamorphic buffer layer and then fabricated. The metamorphic buffer layer is InP - employed because of its high thermal conductivity to minimize device heating. An f/sub /spl tau// and f/sub max/ of 268 and 339 GHz were measured, respectively - both records for metamorphic DHBTs. A 70-nm SiO/sub 2/ dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch for increased device yield and reduced base leakage current. The dc current gain /spl beta/ is /spl ap/35 and V/sub BR,CEO/=5.7 V. The collector leakage current I/sub cbo/ is 90 pA at V/sub cb/=0.3 V. These values of f/sub /spl tau//, f/sub max/, I/sub cbo/, and /spl beta/ are consistent with InP based DHBTs of the same layer structure grown on a lattice-matched InP substrate.     

Extraction of the average collector velocity in high-speed "Type-II" InP-GaAsSb-InP DHBTs

In "type-II" NpN InP-GaAsSb-InP double heterostructure bipolar transistors DHBTs), the p/sup +/ GaAsSb base conduction band edge lies /spl Delta/E/sub C/ above the InP collector conduction band: a small ballistic injection energy /spl Delta/E/sub C/ is thus imparted to electrons as they are launched into the collector. The resulting high initial velocity should in principle reduce the collector signal delay time in comparison to the case where thermal electrons are accelerated by the collector electric field alone. We extract the bias dependence of the average collector electron velocity in high-speed InP-GaAs/sub 0.62/Sb/sub 0.38/-InP DHBTs, and find a maximum average velocity reaching 4/spl times/10/sup 7/ cm/s across a 2000 /spl Aring/ InP collector. This finding provides evidence of the performance advantage afforded by abrupt type-II base/collector (B/C) junctions for collector transport when compared to other B/C junctions.     

An abrupt InP-GaInAs-InP DHBT

We report on the performance of abrupt InP-GaInAs-InP double heterojunction bipolar transistors (DHBTs) with a thin heavily doped n-type InP layer at the base-collector interface. The energy barrier between the base and the collector was fully eliminated by a 4-nm-thick silicon doped layer with N/sub D/=3/spl times/10/sup 19/ cm/sup -3/. The obtained f/sub T/ and f/sub MAX/ values at a current density of 1 mA//spl mu/m/sup 2/ are comparable to the values reported for DHBTs with a grade layer between the base and the collector.     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

Analysis and design of injection-locked LC dividers for quadrature generation

Injection-locked LC dividers for low-power quadrature generation are discussed in this paper. Modeling the circuits as regenerative frequency dividers leads to very simple analytical expressions for the locking band, phase deviation from quadrature and phase noise. Maximizing the ratio between the injected and the biasing current is beneficial to all the above parameters whereas reducing the tank quality factor improves locking band and quadrature accuracy, though at the expense of current consumption, for given output amplitude. To validate the theory, experiments have been carried on a 0.18-/spl mu/m CMOS direct conversion IC, embedding an injection-locked quadrature generator, realized for the Universal Mobile Telecommunication System. Frequency locking range as large as 24% and phase deviation from quadrature around 0.8/spl deg/ are measured while each divider consumes 2 mA. The phase noise of the quadrature generator is determined by the driving oscillator phase noise because the dividers contribution is easily made negligible up to hundreds of megahertz offset.     

High bandwidth and low-leakage current InP-In/sub 0.53/Ga/sub 0.47/As-InP DBHTs on GaAs substrates

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on GaAs substrates. A 284-GHz power-gain cutoff frequency f/sub max/ and a 216-GHz current-gain cutoff frequency f/sub /spl tau// were obtained, presently the highest reported values for metamorphic HBTs. The breakdown voltage BV/sub CEO/ was >5 V while the dc current gain /spl beta/ was 21. High thermal conductivity InP metamorphic buffer layers were employed in order to minimize the device thermal resistance.     

A new method for pHEMT noise-parameter determination based on 50-/spl Omega/ noise measurement system

A new method for determining the four noise parameters of pseudomorphic high electron-mobility transistors (pHEMTs) based on a 50-/spl Omega/ noise measurement system without a microwave tuner is presented. The noise parameters are determined based on the noise correlation matrix technique by fitting the measured noise figure of the active device. On-wafer experimental verification up to 26 GHz is presented and a comparison with a tuner-based method is given. The scaling rules for noise parameters have also been determined. Good agreement is obtained between simulated and measured results for 2/spl times/20 /spl mu/m, 2/spl times/40 /spl mu/m, and 2/spl times/60 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) 0.25-/spl mu/m double-heterojunction /spl delta/-doped pHEMTs.     

10-GHz power performance of a type II InP/GaAsSb DHBT

Type-II InP/GaAsSb double heterojunction bipolar transistors (DHBTs) were fabricated and microwave power performance was measured. For an InP collector thickness of 150 nm, the DHBTs show a current gain of 24, low offset voltages, and a BV/sub CEO/>6V. The 1.2/spl times/16 /spl mu/m/sup 2/ devices show f/sub T/=205GHz and f/sub MAX/=106GHz at J/sub C/=304 kA/cm/sup 2/. These devices delivered 12.6 dBm to the load at P/sub AVS/=3.3 dBm operating at 10 GHz, yielding a power-added efficiency of 41% and G/sub T/=9.3 dB.     

Exact BER computation of generalized hierarchical PSK constellations

We obtain in this paper generic expressions in M for the exact bit-error rate of the generalized hierarchical 2/4//spl middot//spl middot//spl middot//M-phase-shift keyed constellations over additive white Gaussian noise (AWGN) and fading channels. For the AWGN case, these expressions are in the form of a weighted sum of Pawula F-functions and are solely dependent on the constellation size M, the carrier-to-noise ratio, and a constellation parameter which controls the relative message importance. The mathematical expressions are illustrated with some select numerical examples.     

An approach to determine small-signal model parameters for InP-based heterojunction bipolar transistors

A new method for the extraction of the small-signal model parameters of InP-based heterojunction bipolar transistors (HBT) is proposed. The approach is based on the combination of the analytical and optimization technology. The initial values of the parasitic pad capacitances are extracted by using a set of closed-form expressions derived from cutoff mode S-parameters without any test structure, and the intrinsic elements determined by using the analytical method are described as functions of the parasitic elements. An advanced design system is then used to optimize only the parasitic parameters with very small dispersion of initial values. Good agreement is obtained between simulated and measured results for an InP HBT with 5/spl times/5 /spl mu/m/sup 2/ emitter area over a wide range of bias points up to 40 GHz.     

Accurate Analysis Equations and Synthesis Technique for Unilateral Finlines

Accurate analysis equations and synthesis techniques are presented for unilateral finlines, valid over a wide range of structural parameters and substrate dielectic constants (1/spl les/epsilon/sub r//spl les/3.75). These expressions are usable for computing the cutoff wavelength to within +-0.6 percent, the guided wavelength to within +-2 percent, and the characteristic impedance (based on the power-voltage definition) to within +-2 percent, of the spectral-domain method, over the normalized frequency range 0.25/spl les/b/lambda/spl les/0.6.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

A 5-6-GHz bipolar quadrature-phase Generator

A wide-band fully monolithic quadrature-phase generator is implemented. It consists of a bipolar frequency doubler with differential outputs and a regenerative divider with 5 mV/sub rms/ maximum sensitivity. Measured residual phase noise is 相似文献   

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.     

Noise analysis and characterization of a sigma-delta capacitive microaccelerometer

This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop.     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

Design of double-sampling /spl Sigma//spl Delta/ modulation A/D converters with bilinear integrators

Double-sampling techniques allow to double the sampling frequency of a switched capacitor /spl Sigma//spl Delta/ analog-to-digital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator's performance. The fully floating double-sampling integrator is an interesting building block to be used in such a double sampling /spl Sigma//spl Delta/ modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don't have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for double-sampling /spl Sigma//spl Delta/ modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.