高电流增益SiC BMFET功率特性的优化研究

研究了栅电流及结构参数对SiC双极模式场效应晶体管(BMFET)功率特性的影响。仿真研究的结果表明,SiC BMFET器件的开态电阻和电流增益都会随着栅电流的上升而显著下降。沟道掺杂浓度越低,沟道宽度越窄,双极模式调制器件开态电阻的效果越明显,但同时电流增益会降低。相比于单极模式SiC结型场效应晶体管(JFET),SiC BMFET可以显著提升器件的FOM优值,降低器件功率特性对结构参数的敏感度,同时降低了常关型器件的设计难度。     

SiC JFET功率特性的仿真与优化

建立了常关型SiC结型场效应晶体管(JFET)功率特性的数值模型,研究了不同的结构和材料参数对器件功率特性的影响。仿真结果显示,沟道层、漂移层等各层的厚度及掺杂浓度对器件的开态电阻和击穿电压都有明显的影响;采用电流增强层可以明显提高器件的功率特性。研究结果表明,对SiC JFET的结构参数进行优化,可以有效提高器件的优值(FOM)。     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

SiC半导体材料与器件（2）

随着SiC单晶和薄膜制备技术日趋成熟以及相关器件工艺的显著进展,各种SiC器件如pn结与肖特基势垒整流器、JFET、MESFET、增强/耗尽型MOSFET、SiC-Si异质结高频双极晶体管(HBT)、高效太阳能电池等相继出现,Bhatnagar等人经计算分析,指出SiC功率器件(肖特基整流管,VMOSFET)相应同类Si器件的极大优越性在于SiC器件的导通电阻为相应Si器件的几百分之一,加之良好的散热性能,在同样封装条件、结温要求下、SiC功率器件的芯片面积仅为Si器件的二十分之一,从而会部分抵消材料制备等引入的较高成本.尽管SiC器件距商品化尚有一段距离,但已展现出诱人的发展前景.     

高压SiC JFET研究进展

利用自主生长的SiC外延材料,采用干法刻蚀μm级密集深槽工艺技术和高能、高剂量离子注入结合高温激活退火方法,进行SiC电力电子JFET器件的开发,研制出常开型、常关型SiC JFET器件,反向阻断电压都达到1 700V,正向电流达3.5A。常开型JFET的夹断电压在-1.7V,最大跨导Gm为0.52S,比导通电阻最小到4.6mΩ.cm2;常关型JFET的夹断电压在0.9V,最大跨导Gm为1.07S,比导通电阻最小到4.2mΩ.cm2。常开型与常关型器件的栅流开启时栅电压差距小,常开型VG=3.5V时,栅流开始出现,常关型VG=3.3V时,栅流开始出现。     

SiC BMFET开关特性的仿真研究

研究了不同栅电流和负载类型的沟槽注入结构SiC BMFET的开关特性。仿真结果表明,栅区注入的少子集中分布在沟道区域,可以有效提升沟道区域的电导率,也有利于器件的快速开关。当栅电流为10 A/cm²时,器件的开态电阻比单极模式下降低了近30%,开关时间为1.76 μs。当负载含电感时,与单极模式相比,双极模式下的开关时间并未明显延长,但电流和电压过冲小得多。     

用于智能功率集成电路的PTG-LDMOST

提出一种用于智能功率集成电路的基于绝缘体上硅(SOI)的部分槽栅横向双扩散MOS晶体管(PTG-LDMOST)。PTG-LDMOST由传统的平面沟道变为垂直沟道,提高了器件击穿电压与导通电阻之间的折衷。垂直沟道将开态电流由器件的表面引向体内降低了导通电阻,而且关态的时候耗尽的JFET区参与耐压,提高单位漂移区长度击穿电压。仿真结果表明:对于相同的10微米漂移区长度,新结构的击穿电压从常规结构的111V增大到192V,增长率为73%。     

横向增强型双侧栅结构GaN JFET优化设计

提出了一种新型横向双侧栅结构的GaN JFET,并通过SILVACO软件对器件的沟道宽度、沟道电子浓度和p-GaN空穴浓度进行了优化,得到了阈值电压和输出电流与器件参数之间的变化规律,通过参数优化得到了增强型GaN JFET的结构参数条件。随后对设计的横向双侧栅结构增强型GaN JFET器件进行了击穿特性研究,发现当沟道长度短至0.5μm时,会出现严重的短沟道效应;当沟道长度大于1μm后,器件击穿电压由栅极与漏极间寄生PN结反向击穿决定,与沟道长度无关;采用RESURF (Reduced surface field)终端结构可以显著提升器件击穿电压,优化后的增强型GaN JFET器件击穿电压超过1 200 V。此外,采用p型GaN缓冲层替代n型GaN缓冲层,能够有效提高器件的栅控能力。     

6.5kV,25 A 4H-SiC功率DMOSFET器件

<正>与硅IGBT相比,SiC高压功率DMOSFET器件的导通电阻和开关损耗更低,工作温度更高,在智能电网的应用中具有巨大的应用前景。南京电子器件研究所研制出一款6.5kV25ASiC功率DMOSFET器件。建立了高压SiC DMOSFET仿真模型并开展元胞结构设计,通过采用低界面态密度栅极氧化层制备以及JFET区选择掺杂等先进工艺技术,在60μm厚外延层上制备了6.5 kV SiC DMOSFET,芯片有源区尺寸37 mm~2。该器件击穿电压大于6.9 kV,导通电流大于25 A,峰值有效沟道迁移率为23 cm~2/(V·s),比导通电阻降低到44.3 mΩ·cm~2,缩小了与国际先进水平的差距。     

一种JFET区域具有N型重掺杂的1200 V碳化硅浅槽平面MOSFET器件的设计与优化北大核心

介绍了一种在JFET区域采用浅槽N型重掺杂降低器件比导通电阻与开启损耗的1 200 V碳化硅平面栅MOSFET器件。采用浅槽结构设计，减小了器件栅源电容CGS及栅漏电容与栅源电容比值CGD/CGS,降低了器件的开启损耗。浅槽下方采用的N型重掺杂使得器件反型层沟道压降明显提高，使器件获得了更低的比导通电阻。仿真结果表明，相比于平面栅MOSFET器件，开启损耗降低了20%;相比于平面栅MOSFET与分裂栅MOSFET,器件比导通电阻分别减小了14%和17%。     

Optimized design of 4H-SiC floating junction power Schottky barrier diodes

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics.Compared with the conventional power Schottky barrier diode,the device structure is featured by a highly doped drift region and embedded floating junction region,which can ensure high breakdown voltage while keeping lower specific on-state resistance,solved the contradiction between forward voltage drop and breakdown voltage.The simulation results show that with optimized structure parameter,the breakdown voltage Can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

4H-SiC双层浮结肖特基势垒二极管温度特性研究

为了增强器件高温条件下的适应性,对4H-SiC双层浮结肖特基势垒功率二极管的温度特性进行了研究.结果表明,当温度变化时,器件的阻断电压、通态电阻、反向漏电流及开关时间等电学性质均要发生一定的变化.作为一种基于浮结技术的sic新器件,通过数值模拟方法对其特征参数进行优化,可使其承载电流能力、阻断特性和开关速度等得到进一步...     

A new 4H-SiC normally off lateral channel vertical JFET with extremely low power losses: source inserted double-gate structure with a supplementary highly doped region

A novel silicon carbide (SiC) normally off lateral channel vertical junction field-effect transistor (LC-VJFET), namely a source-inserted double-gate structure with a supplementary highly doped region (SHDR), was proposed for achieving extremely low power losses in high-power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LC-VJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20% reduction in on-state loss (P/sub on/) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (P/sub sw/) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75% /spl sim/ 95% reduction, by significantly reducing both input capacitance (C/sub iss/) and reverse transfer capacitance (C/sub rss/) of the device.     

Short-channel GaAs FET fabricated like a MESFET but operating like a JFET

Normally-on GaAs field-effect transistors (FETs) having 1 ?m gate lengths and 4 ?m channel lengths were fabricated in structures grown by molecular beam epitaxy (MBE). The unique part of this device is the very thin p+/n+ structure used to replace the conventional Schottky barriers. The device fabrication procedure is identical to that of a Schottky barrier FET (MESFET), but the devices exhibit characteristics similar to that of a junction field-effect transistor (JFET). This new device, the `camel diode gate FET?, is expected to have applications in both logic and power devices.     

Comparison of current-voltage characteristics of n- and p-type 6H-SiC Schottky diodes

Current-voltage (I–V) characteristics of n- and p-type 6H−SiC Schottky diodes are compared in a temperature range of room temperature to 400°C. While the room temperature I–V characteristics of the n-type Schottky diode after turn-on is more or less linear up to ∼100 A/cm², the I–V characteristics of the p-type Schottky diode shows a non-linear behavior even after turn-on, indicating a variation in the on-state resistance with increase in forward current. For the first time it is shown that at high current densities (>125 A/cm²) the forward voltage drop across p-type Schottky diodes is lower than that across n-type Schottky diodes on 6H−SiC. High temperature measurements indicate that while the on-state resistance of n-type Schottky diodes increases with increase in temperature, the on-state resistance of p-type Schottky diodes decreases with increase in temperature up to ∼330 K.     

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.     

A self-aligned quarter-to-half-micrometer buried-gate GaAs junction FET

We present a reliable but simple self-aligned technology to fabricate very short buried-gate (0.25-0.5 µm) GaAs JFET. The device has a buried p-n junction gate to control the channel current, but in particular, there is another Schottky contact connecting with the source to define the real channel length. The transconductance is 180 mS/mm and the gate leakage current density is only about one-hundredth of the conventional MESFET. Furthermore, there is no backgate effect regardless of how close two devices are neighbored. This technology and device structure are especially useful in GaAs integrated circuits.     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.