一种新型的嵌入式Flash存储器介绍

本文介绍了一种嵌入式应用的存储器工作原理.该存储器结构的基本单元为分离栅结构,采用电场增强型隧穿进行擦除操作,利用沟道热电子注入机制进行编程.接着,本文介绍了存储器可靠性方面的问题.最后,介绍了下一带非挥发性存储器的发展状况.     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

一种感应PN结隧穿场效应晶体管

提出了一种在源区形成感应PN结的隧穿场效应晶体管,利用Silvaco TCAD对器件的工作原理进行了验证,并仿真分析了器件的静态电学特性以及动态特性。结果表明,这种结构的TFET具有低的亚阈值斜率(51mV/dec.)、高的开态电流(5.88μA/μm)、高的开/关态电流比(ION/IOFF为107)以及低至9ps的本征延迟时间,表明利用该结构的TFET器件有望构成高速低功耗逻辑单元。     

嵌入式存储器内建自测试的一种新型应用

当今,嵌入式存储器在SoC芯片面积中所占的比例越来越大,成为SoC芯片发展的一个显著特点。由于本身单元密度很高,嵌入式存储器比芯片上面的其它元件更容易造成硅片缺陷,成为影响芯片成品率的一个重要因素。本文对采用MARCH-C算法的嵌入式存储器内建自测试进行了改进,实现了对嵌入式存储器故障的检测和定位,能够准确判断故障地址和故障类型,使嵌入式存储器故障修复更加快捷、准确,同时达到故障覆盖率高、测试时间短的目的。     

嵌入式系统中存储器性能研究

动态随机存储器是嵌入式系统的一个重要组成部分,而动态随机存储器故障是嵌入式系统故障的一个主要原因之一。在此从动态随机存储器的结构和失效模型出发,有针对地提出了用于检测性能的数据和读写方式,实验证明通过提出的检测方法能够有效地找出潜在的存储器故障,从而能够为嵌入式系统设计人员提供改善系统性能的方法和途径。     

一种改善三栅分栅快闪存储器耐久性能的方法

基于三栅分栅闪存在擦除操作F-N隧穿停止时界面电场恒定的特性,提出一种动态擦除电压模型,该模型基于稳定循环操作后浮栅电位的理念,通过实时可监测的浮栅电位值来动态调节闪存器件擦除操作的工作电压,提升了三栅分栅闪存器件的耐久特性.从实际监测数据可以看出,为保持稳定的浮栅电位,浮栅擦除操作电压随着编程/擦除循环次数先快速增加,并在循环10 000次后逐渐趋于饱和.相对于传统的恒擦除电压方式,通过这种新的动态擦除电压方式,器件在经过100 000次循环编程/擦除后阈值电压的漂移从原始1.2V降低为小于0.4V,优化了器件耐久性的工作窗口约0.8V.     

动态随机存储器IC芯片制造技术的进展与展望

介绍了DRAM 0.1μm特征尺寸理论极限的突破及相关技术进展,以及各种非易失性随机存储器(NVRAM)如FeRAM,相变RAM,MRAM.现今PC中的RAM很快将被NVRAM所取代,从而可缩短PC的启动时间.     

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。     

1.25VRDIMM：动态随机存取存储器

三星电子推出采用30纳米级企业服务器1．25V16GBDDR3RDIMM（RegisteredDualInlineMemoryModule）产品。     

Novel Design for High Speed and Resolution Delta-sigma A/D Converter

The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta- sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching（DEM） and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.     

Drive current boosting of n-type tunnel FET with strained SiGe layer at source

Though silicon tunnel field effect transistor (TFET) has attracted attention for sub-60 mV/decade subthreshold swing and very small OFF current (I_OFF), its practical application is questionable due to low ON current (I_ON) and complicated fabrication process steps. In this paper, a new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60 mV/decade subthreshold swing along with a significant improvement in I_ON. The enhancement in I_ON is achieved by introducing a thin strained SiGe layer on top of the silicon source. Through 2D simulations it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction. It is also found that the body bias does not change the drive current but after body current gets affected. An I_ON of and a minimum average subthreshold swing of 13 mV/decade is achieved for 100 nm channel length device with 1.2 V supply voltage and 0.7 Ge mole fraction, while maintaining the I_OFF in fA range.     

嵌入式高速固态存储器的设计

现代的数据处理技术需要较快的数据采样率和较宽的数据带宽,这就要求采用嵌入式高速固态存储器来实时记录海量的数据。介绍了NAND FLASH的选型、嵌入式高速固态存储器的组成原理、现场可编程门阵列(FPGA)的实现逻辑及存储器的性能计算,最后对本设计进行了总结和展望。     

嵌入式高速USB设备接口结构设计

高速度、高可靠性、低功耗的串行系统总线是航天通信领域进一步发展必须解决的一个关键问题.简要地介绍了USB 2.0通信协议的基本原理、系统结构和数据传输,并以此为基础给出具有高可靠性的USB通信系统框架结构.并在此基础上提出具体的方案,经试验此USB设备接口可满足通信的性能要求.     

一种新型的双频高增益天线设计

为了适应现代双频通信系统的要求,该文将褶皱结构的透波增强特性应用于天线设计中,并在中心圆孔处添加环形金属柱,设计了一个双频高增益天线。仿真和测试结果表明,在12.7 GHz和14.4 GHz处,天线的增益分别为12.0 dB和12.9 dB,相对于传统天线分别提高了5.6 dB和6.3 dB。此外,天线的半功率波束宽度(Half Power Beam Width, HPBW)也得到了较好的优化。     

用于TFT-LCD驱动芯片的内置DRAM设计

TFT-LCD驱动芯片中需要较大容量的内置存储器,相对于静态存储电路而言,动态存储电路节省了芯片的面积,有利于芯片成本的降低.文章讨论了用于TFT-LCD驱动芯片内置DRAM的分块设计方法,结合芯片物理特点将其分为左右对称两块.采用改进的3-T结构DRAM存储阵列,省去了伪存储单元,节省了面积,降低了功耗.优化了DRAM的刷新电路,省略了判断信号与RAS和CAS先后顺序的仲裁电路.结合芯片本身的特点设计了行、列译码电路.对于芯片的仿真,采用了模拟验证和形式验证相结合的前端设计验证方法,同时又采用了结构化抽取寄生参数和建立关键路径的后仿真.     

混合参数高灵敏度微波GaAsFET压控振荡器的研制

介绍了 Ｃ 波段低端的 Ｇａ Ａｓ Ｆ Ｅ Ｔ 压控振荡器（ Ｖ Ｃ Ｏ）。这种振荡器采用混合参数设计技术,选用新型场效应晶体管（ Ｆ Ｅ Ｔ）反沟道电路接法。分析了电路工作原理及影响电压调制带宽的诸因素,提出并解决了一些技术难题,给出了测试结果。结果表明这种 Ｖ Ｃ Ｏ 具有较大的优越性。     

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I_on more than double, while the off-state currents I_off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I_on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.     

Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode

In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V.     

一种新型高速电流比较器的研究与设计

针对传统电流比较器速度慢、精度低等问题,提出了一种新型CMOS电流比较器电路。采用CMOS工艺HSPICE模型参数,对该电流比较器的性能进行了仿真,结果表明当电源电压为3．3V,输入方波电流幅度为0．3μA时,电流比较器的延时为5．2ns,而其最小分辨率达0．1nA。该比较器结构简单、速度快、精度高,适合应用于高速高精度电流型集成电路。