基于EDA技术的图像边缘检测协处理器的设计

在嵌入式图形系统处理领域,图像处理的速度问题一直是一个很难突破的设计瓶颈.文章在介绍一种全新的DSP CPLD图像处理系统工作原理的基础上,阐述了一个基于EDA技术的、用FPGA实现的800×600像素的图像边缘检测协处理器的设计,包括边缘检测算法选择、系统的FPGA实现设计和有关仿真结果等.该协处理器的像素处理方式采用全硬件并行及流水线技术,比单独采用单片机和DSP的系统,其处理速度分别提高了400倍和10倍,同时该系统集成在一块集成芯片上,体积小,功耗低,可靠性高,并可现场编程,在线升级.     

基于FPGA＋多DSP的JPEG2000星载遥感图像压缩实现方案

为了满足星载遥感图像压缩的实时性需求,以及最大程度地发挥硬件功效,提出了一种高效的JPEG2000星载遥感图像压缩实现方案.借助流水线和SPMD(Single Program Multiple Data)并行思想,建立了JPEG2000压缩算法实现方案的体系结构,并搭建了基于FPGA和4 DSP的硬件平台.FPGA与4个DSP以独立方式通过EMIF接口相连,数据传输基于抢先式控制;为了便于对DSP调试和管理,4个DSP的仿真接口串成JTAG链结构;为了降低硬件复杂度以及加快DSP的引导速度,设计了HPI并行引导方法.     

基于FPGA的线阵CCD雨滴图像快速连续识别方法

雨滴粒子直径和速度实时测量是雨滴谱参数计算的关键,为了实时、连续得到精确、可靠的统计雨滴样本数据,采用基于高速线阵CCD的光阵排列法对雨滴速度和直径进行非接触测量,通过FPGA构造雨滴图像乒乓操作缓存单元,存储两行连续一维动态雨滴图像,发挥FPGA的并行运算能力,利用FPGA快速实现雨滴动态图像连通域检测及连通域标记算法,进而实现雨滴粒子的直径和速度检测.实验证明,该方法能自动连续测量记录雨滴数量、粒径大小和收尾速度,为雨滴谱参数计算提供可靠样本数据.     

基于矩阵相似变换的并行流水线CRC实现

研究了通用并行化循环冗余校验(CRC)编码结构,分析了限制编码速度提高的主要原因,根据多项式理论推导了并行CRC编码的一般化方法.在此基础上,根据线性代数中的有理标准型理论对编码结构中的反馈运算矩阵进行相似变换,提出了CRC编码的高速流水线并行结构,并设计实现了多种不同并行度下的CRC编码器.设计结果表明,高速流水线并行CRC编码器结构相对于其他结构具有最优的编码速度和最优的时序特性,可以满足高速数据完整性校验的需求.     

基于聚类分析技术的装配流程平衡运行研究

通过测算不同装配流水线上各个工序作业时间,利用聚类分析技术将各流水线按不同作业时间进行聚类,并画出装配时间谱系聚类图.根据聚类分析得出的各流水线作业时间类别及相互类级关系,控制各条流水线上零部件的投放时间及物流速度,使不同流水线上的装配零部件在最短时间相遇,据此达到装配流程平衡运行,提高装配效率.     

自适应光学系统SPGD控制算法的FPGA硬件实现

针对随机并行梯度下降(SPGD)算法实时性强,同时具有一定的灵活性的要求,本文提出了一种基于FPGA的SPGD算法硬件实现方法.该方法首先划分了各功能模块,然后对关键模块进行了实时化处理,并使用"流水线"和RAM技术设计了可升级和扩展的变形镜控制模块.最后将该算法实现并应用到6l单元自适应光学激光实验中,结果表明本文的设计可使用不同的性能指标实现变形镜的SPGD算法闭环控制,并能同时完成倾斜镜的控制,达到了实时性和灵活性的要求.     

各向异性模型图像增强算法的FPGA高速实现

针对Perona-Malik模型图像增强算法运行在计算机CPU上无法满足算法的实时性要求的问题,基于FPGA设计了一种改进型Perona-Malik模型图像增强算法的硬件加速结构.该硬件加速结构采用行缓存实现对部分图像的缓存操作;同时通过提取出参数查找表的方式,并使用梯度的计算结果为索引,降低了硬件结构的复杂度;计算过程中采用补码和定点小数,保证了计算结果的准确性;此外采用3级流水线处理方式,增加了该硬件结构的吞吐量.实验结果表明:8次迭代处理后,在与软件处理效果相近的情况下,一帧256×256图像处理时延约为0.67 ms,满足实时处理的需求,是计算机CPU实现速度的近300倍.     

基于V93000的现场可编程门阵列测试时间优化方法

对于现场可编程门阵列FPGA,测试配置时间远大于加测试向量的时间,为实现FPGA快速配置测试,本文提出了一种FPGA测试时间优化方法:采用Advantest公司V93000自动测试设备,通过在一个周期内加载4行配置向量对电路配置比特流的测试时间进行优化(即4X配置方式),并结合FPGA多帧写位流压缩方法对电路测试配置的编程加载时间进行优化;以Xilinx公司Virtex-7系列FPGA-XC7VX485T为例进行了测试验证,测试数据表明:采用V93000SoC测试系统的4X配置方式,FPGA的单次配置时间减少了74.1%;为了满足量产测试对于测试时间的要求,进一步提出V93000的4X配置方式与FPGA的位流压缩相结合的方法,FPGA的单次配置时间由1.047s减少到47.834ms,测试时间压缩了95.5%.该方法有效减少了FPGA单次测试时间,提高了在系统配置速度.     

Design and verification of a JPEG2000 VLSI architecture of bit plane coder using 2-branch coding path

研究了JPEG2000中位平面编码算法,提出了适用于显著性传播过程和清除过程的叉形编码路径,使得完成一个4×n条带编码的路径长度缩减为标准的(n+1)/(2n).基于该编码路径,设计了两窗口流水线硬件编码结构,该结构通过两个编码窗口流水线滑动在平均每个时钟内完成16个样本点的位平面编码,关键模块采用组合电路实现,避免了时钟消耗和复杂控制,可在位平面间并行进行.给出了系统的整体VLSI架构.FPGA验证结果表明,系统时钟可综合到203.083MHz,处理512×512的灰度图像达276fps,可满足图像实时处理的要求.     

在普通瓦楞纸板自动流水线上加装六层复合智能装置

目的 在现有普通瓦楞流水线的基础上实现六层复合瓦楞纸板的生产.方法 复合部分,基于传统瓦楞上胶构思,利用线辊上胶复合原纸,优化上胶量的控制.衔接智能控制部分,依据原纸材质、整机车速的不同要求对供电方式、数显模块、上胶量控制等方面进行设计改善.结果 复合设备可在现有的瓦楞纸板生产流水线中增设,实现高强度六层复合瓦楞纸板的...     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

基于 NAND Flash 的嵌入式文件系统设计

主要介绍了针对 NAND Flash 型存储器设计的嵌入式文件系统. 其硬件平台是为了顺应多功能、大容量集成化存储的需求而开发的基于 ADSP-BF532 芯片与 NAND Flash 结合的高性能嵌入式存储系统. 此存储系统采用了多片并行流水的存储模式,开发出独特有效的闪存管理技术与改良的文件系统,通过设置访问权限实现多用户管理,使得处理器、存储器以及文件管理层软件的多方优势得以充分发挥.     

基于FPGA的铅笔画绘制算法结构设计及优化

由于FPGA同时具有硬件的快速和软件的灵活两方面的优点,这一平台在图像和视频处理方面的应用日益广泛。然而就目前来说,FPGA主要用于真实感图像或视频的处理,而把FPGA应用于非真实感绘制的研究还是一片空白,因此提出了一种基于FPGA把输入图像处理为铅笔画输出或把输入实时视频处理为铅笔画视频输出的方法。在此方法的探索中,先对铅笔画生成算法作并行性分析,得到适用于FPGA的算法,再在此基础上应用硬件特有的流水线乘法技术进行优化以提高硬件系统的处理速度。     

基于嵌入式系统的NANDFlash坏块处理和FMM实现

随着嵌入武产品的不断发展,对存储设备的要求也越来越高.本文以NANDFlash为例,介绍了大容量NANDFlash在嵌入式系统中的设计与应用,并提出了一种消除文件写入NANDFlash时出现坏块影响的方法.同时对基于NANDFlash的管理软件FMM的实现算法进行了优化,提高了效率和性能.     

Integrated microfluidic electrophoresis system for analysis of genetic materials using signal amplification methods

An isothermal signal amplification technique for specific DNA sequences, known as cycling probe technology (CPT), was performed within a microfluidic chip. The presence of DNA from methicillin-resistant Staphylococcus aureus was determined by signal amplification of a specific DNA sequence. The microfluidic device consisted of four channels intersecting to mix the sample and reagents within 55 s, as they were directed toward the reactor coil by electrokinetic pumping. The 160-nL CPT reactor occupied approximately 220 mm2. Gel-free capillary electrophoresis separation of the biotin- and fluorescein-labeled probe from the probe fragments was performed on-chip following the on-chip reaction. An off-chip CPT reaction, with on-chip separation gave a detection limit of 2 fM (0.03 amol) target DNA and an amplification factor of 85,000. Calibration curves, linear at <5% probe fragmentation, obeyed a power law relationship with an argument of 0.5 [target] at higher target DNA concentrations for both on-chip and off-chip CPT reaction and analysis. An amplification factor of 42,000 at 250 fM target (25,000 target molecules) was observed on-chip, but the reaction was approximately 4 times less sensitive than off-chip under the conditions used. Relative SD values for on-chip CPT were 0.8% for the peak migration times, 9% for the area of intact probe peak, and 8% for the fragment/probe peak area ratio.     

New strategies for fast ADC circuits

A modified strategy for successive approximation is discussed. A four-bit multilevel converter of one-cycle conversion time is first described. Approximation is carried over at two levels handling two bits at a time. This results in a relative speed improvement of five times over the conventional method for the four-bit scheme. The four-bit multilevel converter is modified for flash conversion. Experimental results for the four-bit flash converter are presented. Eight-bit converters, as extensions of the four-bit schemes presented, are also proposed. Practical results of the four-bit multilevel flash converter display good linearity. The worst-case conversion time was found to be about 650 ns     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon memory device with different tunneling oxide thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.     

基于复用模型的高速光电扫描仪性能的改进研究

提出了一种基于FPGA和DDRⅡ的JPEG图像压缩模式。在此基础上完成了A3高速光电扫描仪的设计与实现,解决了高速扫描仪中硬件资源与扫描速度相互制约的问题。通过内外存储器流水式复用模型,在降低片上RAM消耗的同时构建灵活、快速的大数据量存储与传输模式。采用高效的分时复用数据链路实现JPEG图像压缩,进一步提高硬件模块的压缩和传输速度。对采用中低端FPGA芯片设计的A3高速扫描仪的测量结果表明,在300 dpi分辨率下扫描A3幅面纸张的速度可达140面/min,扫描延时小于1 ms,压缩前后峰值信噪比高达86.9dB,完全满足高端高速扫描仪的要求。该模式的实现极大地降低了高端高速光电扫描仪对于硬件资源的要求,也可推广应用到其它幅面的高速光电扫描仪中。     

Multichannel holographic recording method for three-dimensional displays

A multichannel holographic recording method is presented for three-dimensional (3D) displays, utilizing pixel-based recording instead of image-based recording in order to realize parallel processing. The proposed approach is composed of two main stages. In the first stage, each two-dimensional (2D) image acquired from multiple viewpoints is partitioned by holographic recording channels (HRC) into nonoverlapping subimages. In the second stage, the corresponding pixels of the subimages are rearranged to constitute an encoding image. The encoding images are recorded simultaneously by each HRC, respectively, so the recording speed is improved significantly. The experimental results have demonstrated that the three-channel system is feasible and the full-parallax hologram reconstructed with white light is acceptable in quality. The three-channel system saves approximately 60% of the recording time in comparison with the single-channel system. More importantly, the proposed method can accomplish a large-scale final hologram composed of multichannel holograms without sacrificing the hologram quality. Several 3D imaging applications such as medical diagnosis and advertisements could benefit from this research.     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon devices with a separated double-gate saddle-type structure

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.