一种低功耗、高稳定性的无片外电容线性稳压器

本文研究并设计了输出电压3.3V,最大输出电流为150mA的CMOS无片外电容的低压差线性稳压器(Off-chipcapacitor-free Low-dropout Voltage Regulator,LDO).该LDO采用了NMC(Nested Miller Compensation)频率补偿技术保证了系统的稳定性.另外,采用大电容环路和SRE(Slew Rate Enhancement)电路抑制输出电压的跳变,改善了瞬态响应.电路采用了低功耗设计技术.采用CSMC 0.5μm CMOS混合信号工艺模型仿真表明:整个LDO的静态电流仅为3.8μA;最差情况下的相位裕度约为88.50;在5V工作电压下,当负载电流在1μs内从150mA下降到1mA时,输出电压变化仅为140mV;在负载电流150mA的情况下,当电源电压在5μs内从3.5V跳变至5V时,输出电压变化也仅为140mV.     

一种快速瞬态响应无输出电容LDO的研究与设计

设计了一种基于自适应偏置放大器的具有快速瞬态响应的无输出电容LDO.自适应偏置放大器在发生负载瞬态响应时能够调节自身偏置电流以提供较大的输出电流来增加摆率;瞬态响应提升电路通过减小负载电容充放电电流而减小了输出电压的建立时间;通过并联反馈补偿来提高环路的稳定性.仿真结果表明,所设计的无输出电容LDO最大输出电流200mA,最小跌落电压200mV,静态电流仅16μA,全负载正负阶跃变化响应时间分别为2.5μs和3.5μs.     

大电流负载的片上LDO系统设计

 本文分析了传统大电流负载的LDO(Low-dropout Regulator)系统实现系统稳定性和瞬态响应提高的局限性,在此基础上,提出了一种片内集成的瞬态响应提高技术.此技术无需外挂电容和等效串联电阻(Equivalent Series Resistor,ESR),即能使系统在全负载范围内保持稳定性和良好的纹波抑制能力.仿真结果表明,系统空载时,静态电流为64μA,且最大能提供800mA的负载电流,1KHz时的电源抑制比达到-60dB,当负载电流以800mA/5μs跳变时,最大下冲电压为400mV,上冲电压为536mV,恢复时间分别只需6.7μs和12.8μs,版图面积约为0.64mm².     

一种快速瞬态响应的无片外电容型LDO

设计了一种快速瞬态响应的无片外电容型LDO。采用高增益高带宽的超级跨导结构(STC)的误差放大器,利用动态偏置技术与电容耦合技术,极大地增强了摆率。引入额外的快速响应环路,进一步提升了瞬态响应速度。基于0.18 μm CMOS工艺进行设计。结果表明,该LDO的最低供电电压为1 V,漏失电压仅为200 mV,可提供最大100 mA的负载电流,能在最大输出电容为100 pF、最低负载为50 μA的条件下保证电路稳定。负载电流在0.5 μs内由50 μA跳变至100 mA时,LDO输出导致的过冲电压和下冲电压分别为200 mV和306 mV。     

基于电容倍增技术的LDO补偿方法

设计了一种低静态电流、高稳定性的LDO稳压器.该电路使用电容倍增技术进行频率补偿,减小了补偿电容值,节省了芯片面积,在负载电流0.1mA和150mA时具有较好的相位裕度.电路采用XFAB 0.6μm CMOS工艺模型,最终设计的LDO电路静态功耗17μA,最大驱动电流150mA.使用10μF的负载电容,在负载电流变化率为150mA/100μs时,最大过冲为22mV(1.83%).     

基于高压摆率误差放大器和摆率增强电路的无片外电容LDO

基于0.35μm CMOS工艺设计了一款无片外电容低压差线性稳压器(cap-free LDO),通过误差放大器组成的环路控制稳态误差,通过摆率增强电路构成的环路改善瞬态响应。该LDO输出电压为1.72V,压差80mV,最大输出电流50mA。测试结果显示:负载电流(IL)在0.5μs内瞬变50mA时,俯冲电压和过冲电压均为80mV左右,重回稳态的时间均小于1.5μs。     

基于阻尼系数控制频率补偿的无电容型LDO设计

基于级间密勒补偿技术,产生一个低频主极点,并通过阻尼系数控制(DFC)单元调节两个次主极点略高于单位增益频率(UGF),使得无电容型LDO开环传递函数中在UGF内只有一个极点,从而保证环路稳定性,同时又优化了系统的动态响应.基于该结构,采用HHNEC 0.25μm CMOS工艺,设计了一个1.8V 100mA的适合SoC应用的无电容型LDO.其电压降为50mV,在50μA到100mA的负载电流范围内,开环传递函数相位裕度高于55度,瞬态电压过冲值低于140mV,负载电流在最大值与最小值之间阶跃变化时,最大恢复时间为3μs,系统静态电流为40μA.     

一种具有瞬态增强的无片外电容型LDO

提出了一种稳定性高、瞬态特性良好、无片外电容的低压差线性稳压器(LDO)。采用推挽式微分器检测负载瞬态变化引起的输出电压变化,加大对功率管栅极寄生电容的充放电电流,增强系统的瞬态响应能力;在误差放大器后接入缓冲级,将功率管栅极极点推向高频,并采用密勒电容进行频率补偿,使系统在全负载范围内稳定。基于TSMC 65 nm CMOS工艺进行流片,核心电路面积为0.035 mm²。测试结果表明,最低供电电压为1.1 V时,压降仅为100 mV,负载电流1 μs内在1 mA和150 mA之间跳变时,LDO的最大输出过冲电压与下冲电压分别为200 mV和180 mV。     

基于负载电流动态泄放技术的LDO线性稳压器

通过对LDO瞬态响应的分析,基于负载电流动态泄放技术,提出一种新型LDO线性稳压电路,减小了负载电流阶跃变化对输出电压的影响,从而改善了系统的瞬态响应特性.采用0.18μm CMOS工艺模型进行仿真.结果表明,负载电流从1mA到120mA阶跃变化时,输出电压负向过冲减小60.1mV,恢复时间缩短33.4μs;从120mA到1mA阶跃变化时,输出电压正向过冲减小47mV,恢复时间缩短214.3μs.     

一种基于密勒倍增的高性能LDO的设计

基于零极点跟踪技术,提出一种新的LDO频率补偿架构.利用密勒电容倍增原理和零极点跟踪技术,在很小的补偿电容面积下使LDO获得全负载范围内的环路稳定.摆率增强电路的应用使系统具有优越的负载瞬态调整性能.基于0.5 μm标准CMOS工艺,对LDO进行仿真验证.结果表明,系统空载下,静态电流为32 μA,且能提供最大200 mA的负载电流;在输出电容为2.2 μF、负载电流以200 mA/10 ns突变时,最大下冲电压仅为10 mV,没有明显的上冲.     

采用增强型AB跟随器的快速响应LDO

设计了一种采用增强型AB跟随器作为缓冲器的快速响应LDO.利用跟随器的动态电流提高能力,显著地改善了误差放大器对功率MOS管寄生大电容的驱动;同时,由负反馈引起的阻抗降低效应将功率管的寄生电容极点推到了更高的频率,提高了环路的相位裕度.采用TSMC0.35-μm CMOS工艺进行仿真,当负载电流在0.1μs内从1 mA跳变到50 mA以及从50 mA跳变到1 mA时,相对于同等条件下的源跟随器LDO,输出峰值分别减少4 mV和46 mV,且稳定时间只需要0.2 μs和0.5 μs.     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out(LDO) regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV(0.7%) overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.     

A 50‐mA 1‐nF Low‐Voltage Low‐Dropout Voltage Regulator for SoC Applications

In this paper, we present a low‐voltage low‐dropout voltage regulator (LDO) for a system‐on‐chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1‐nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop‐out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.     

一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.     

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.