亚微米CMOS电路中VDD-VSS ESD保护结构的设计

文章根据一个实际电路中ESD保护结构的设计,引出了一种亚微米CMOS IC中基于RC延迟而设计的VDD-VSS之间直接电压钳位结构,并结合例子中此结构前后的修改优化对该结构进行了详细的仿真分析。进一步比较了两种VDD-VSS电压钳位结构的优劣。最后阐述了亚微米CMOS电路的设计中,全芯片ESD结构的有效设计。     

基于SCR的全芯片ESD保护设计

随着集成电路特征尺寸的减小,集成电路对ESD的要求越来越高,同时集成电路面积和引脚数量的增加,使得全芯片的ESD保护成为挑战。SCR器件相对于其他器件,具有相同面积下最高的ESD保护性能。文章以SCR保护器件为基础,介绍一种新型的ESD保护架构——ESD总线。从全模式和混合电压芯片的ESD保护出发,进而提出了全芯片ESD保护结构,针对现代集成电路芯片引脚不断增多的特点,以及系统集成带来的多电压模式问题,提出了使用ESD总线结构的保护方案来实现全芯片的ESD保护。     

用于16通道16位D/A转换器的全芯片ESD保护电路

ESD保护电路是保证集成电路可靠性的重要电路之一。具有较大芯片面积和较多电源域的集成电路给全芯片ESD保护电路的设计带来挑战。基于0.6 μm CMOS工艺,设计了一种全芯片ESD保护电路,应用于5个电源域的16通道16位D/A转换器中。该D/A转换器的抗ESD能力大于2 000 V,芯片尺寸为9 mm × 9 mm。     

一种CMOS新型ESD保护电路设计

金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。     

CMOS片上电源总线ESD保护结构设计

随着集成电路制造技术的高速发展,特征尺寸越来越小,静电放电对器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了三种常见的CMOS集成电路电源总线ESD保护结构,分析了其电路结构、工作原理和存在的问题,进而提出了一种改进的ESD保护电源总线拓扑结构.运用HSPICE仿真验证了该结构的正确性,并在一款自主芯片中实际使用,ESD测试通过±3 000 V.     

一种CMOS IC片上电源ESD保护电路

随着集成电路工艺的高速发展,特征尺寸越来越小,静电放电对CMOS器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了两种常见的CMOS集成电路电源系统ESD保护电路,分析了它们的电路结构、工作原理和存在的问题,进而提出了一种改进的电源动态侦测ESD保护电路.使用HSPICE仿真验证了该电路工作的正确性,并且在一款自主芯片中使用,ESD测试通过士3000 V.     

一种改进型MLSCR-ESD结构设计分析

集成电路中半导体器件的特征尺寸不断减小,集成电路对ESD的冲击更加敏感。静电防护成为集成电路中最重要的可靠性指标之一,ESD保护结构也成为芯片设计中的难题。随着集成电路规模的增大,芯片引脚增多,大量面积被用于ESD保护电路,导致成本提高。可控硅结构的ESD保护器件相比其他已知保护结构具有最高的单位面积ESD性能,因此成为低成本片上ESD设计方案的首选。针对改进型横向SCR (MLSCR,又称N+桥式SCR)的ESD保护结构,对其关键特性指标结合理论分析与实验数据进行分析。基于某0.18μm 5 V CMOS工艺的流片结果,对SCR结构的工作原理以及关键的触发电压、保持电压参数进行说明,并提出改进方案。     

基于SCR的双向ESD保护器件研究

可控硅整流器件(SCR)结构用于集成电路的静电放电(ESD)保护具有提高保护效率,减小芯片面积和降低寄生参数的优点.对基于SCR的双向ESD保护器件进行了研究;建立了一种ESD保护器件仿真设计平台,对该器件的结构、关键参数和性能进行了系统的仿真和优化.得到的改进器件不仅对ESD人体模型(HBM)的保护性能好,引入电路的寄生效应小,而且ESD保护的各关键性能参数也可以方便地进行调整.     

CMOS SoC芯片ESD保护设计

本文提出从器件失效功率的角度,解释CMOS SoC（System On Chip）芯片的ESD（ElectrostaticDischarge）失效原因,总结了CMOS集成电路（IC）的多种ESD失效模式,研究了多电源系SoC芯片的ESD保护设计方法,提出了SoC芯片的ESD保护设计流程。     

深亚微米CMOS IC全芯片ESD保护技术

CMOS工艺发展到深亚微米阶段,芯片的静电放电(ESD)保护能力受到了更大的限制。因此,需要采取更加有效而且可靠的ESD保护措施。基于改进的SCR器件和STFOD结构,本文提出了一种新颖的全芯片ESD保护架构,这种架构提高了整个芯片的抗ESD能力,节省了芯片面积,达到了对整个芯片提供全方位ESD保护的目的。     

混合信号IC的ESD保护电路设计

从电路设计的角度,介绍了混合信号IC的输入、输出、电源箝位ESD保护电路.在此基础上,构建了一种混合信号IC全芯片ESD保护电路结构.该结构采用二极管正偏放电模式,以实现在较小的寄生电容情况下达到足够的ESD强度;另外,该结构在任意两个pad间均能形成ESD放电通路,同时将不同的电源域进行了隔离.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

0.6μm SOI NMOS器件ESD性能分析及应用

ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...     

Analysis of ESD discharge current distribution and area optimization of VDMOS gate protection structure

The VDMOS Electrostatic Discharge (ESD) protection structure using back-to-back connected zener diode on poly-Si film has been studied. The study reveals that there exists an effective range for the values of the current distribution resistors and optimal size of the zener diode to maximize the ESD protection. A model is proposed to analyze the effect of the current distribution resistors and the size of the zener diode. We also propose a design rule for optimizing the size of the ESD protection structure under the constraint of ESD voltage. The presented analytical model is validated with experimental measurements.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

The mirrored lateral SCR (MILSCR) as an ESD protection structure:design and optimization using 2-D device simulation

A methodology for the application of two-dimensional (2-D) device simulation to electrostatic discharge (ESD) events is presented. Correlation of ESD simulation results with experimental data is illustrated using a grounded base n-p-n transistor. It is shown that device simulation is essential for understanding complex ESD failure mechanisms. The application of the methodology to the design of a new ESD protection structure, the mirrored lateral silicon controlled rectifier (MILSCR), is then discussed. Experimental results show that the MILSCR provides a very efficient double-polarity ESD protection. Finally, device simulation is used to optimize this structure for smart-power applications. In particular, holding currents as high as 134 mA are achieved, allowing one to cope with the latchup danger during normal operation     

一种系统级封装的ESD保护技术

介绍了一种系统级封装(SiP)的ESD保护技术.采用瞬态抑制二极管(TVS)构建合理的ESD电流泄放路径,实现了一种SiP的ESD保护电路.将片上核心芯片的抗ESD能力从HBM 2 000 V提升到8 000 V.SiP ESD保护技术相比片上ESD保护技术,抗ESD能力提升效果显著,缩短了开发周期.该技术兼容原芯片封...     

A new pad-oriented multiple-mode ESD protection structure andlayout optimization

This work reports a new multiple-mode pad-oriented electrostatic discharge (ESD) protection structure, which protects input-output pads against ESD pulses of all modes. A unique pad-based quasi-symmetric layout design is devised to improve ESD robustness. The new ESD structure features tunable triggering voltage, low holding voltage, low on-impedance, low leakage (~pA), fast response time (~0.18 ns), and low parasitic effect. It can be placed under a bond pad and consumes little silicon. It passed 14 kV human body model and 15 kV air-gap International Electrotechnical Commission ESD zapping. It was demonstrated in commercial BiCMOS processes and is suitable for multiple-supply mixed-signal, parasitic-sensitive RF and high-pin-count ICs     

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle.