用于电路模拟的4H-SiC MOSFET高温沟道电子迁移率模型

提出了适用于电路模拟的4H-SiC n-MOSFET高温沟道电子迁移率模型.在新模型中,引入了横向有效电场和表面粗糙散射的温度依赖性,电子饱和漂移速度与横向有效电场和温度的关系,以及改进的界面陷阱电荷和固定氧化物电荷库仑散射模型等因素.采用与温度-阈值电压实验曲线拟合的方法,确定了界面态参数和固定氧化物电荷.基于新迁移率模型的模拟结果与实验吻合.     

用于电路模拟的4H-SiC MOSFET高温沟道电子迁移率模型

提出了适用于电路模拟的4H-SiC n-MOSFET高温沟道电子迁移率模型.在新模型中,引入了横向有效电场和表面粗糙散射的温度依赖性,电子饱和漂移速度与横向有效电场和温度的关系,以及改进的界面陷阱电荷和固定氧化物电荷库仑散射模型等因素.采用与温度-阈值电压实验曲线拟合的方法,确定了界面态参数和固定氧化物电荷.基于新迁移率模型的模拟结果与实验吻合.     

非晶IGZO薄膜晶体管开启区电流的解析模型

对非晶In-Ga-Zn-Oxide薄膜晶体管,假设能隙中陷阱态密度呈指数分布,给出了解析的电流模型。运用薄层电荷近似的方法推导陷落电荷和自由电荷表达式,并基于此给出了基于表面势的电流表达式。在此电流表达式的基础上,通过泰勒展开,给出了基于阈值电压的电流表达式。基于表面势和基于阈值电压的电流表达式的计算结果与测量数据相比较,符合得很好。     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

埋氧离子注入对P型部分耗尽SOI电学与低频噪声的影响

针对抗辐照SOI PMOS器件的直流特性与低频噪声特性展开试验与理论研究,分析离子注入工艺对PMOS器件电学性能的影响,并预测其稳定性的变化。首先,对离子注入前后PMOS器件的阈值电压、迁移率和亚阈摆幅进行提取。测量结果表明:埋氧化层离子注入后,器件背栅阈值电压由-43.39 V变为-39.2 V,空穴有效迁移率由127.37 cm2/Vs降低为80.45 cm2/Vs,亚阈摆幅由1.35 V/dec增长为1.69 V/dec;结合背栅阈值电压与亚阈摆幅的变化,提取得到埋氧化层内电子陷阱与背栅界面态数量的变化。随后,分析器件沟道电流噪声功率谱密度随频率、沟道电流的变化,提取γ因子与平带电压噪声功率谱密度,由此计算得到背栅界面附近的缺陷态密度。基于电荷隧穿机制,提取离子注入前后埋氧化层内陷阱态随空间分布的变化。最后,基于迁移率随机涨落机制,提取得到离子注入前后PMOS器件的平均霍格因子由6.19×10-5增长为2.07×10-2,这表明离子注入后器件背栅界面本征电性能与应力稳定性将变差。     

关态应力下 P- MOSFETs的退化

研究了沟长从 0 .5 2 5 μm到 1.0 2 5 μm9nm厚的 P- MOSFETs在关态应力 ( Vgs=0 ,Vds<0 )下的热载流子效应 .讨论了开态和关态应力 .结果发现由于在漏端附近存在电荷注入 ,关态漏电流在较高的应力后会减小 .但是低场应力后关态漏电流会增加 ,这是由于新生界面态的作用 .结果还发现开态饱和电流和阈值电压在关态应力后变化很明显 ,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响 .Idsat的退化可以用函数栅电流 ( Ig)乘以注入的栅氧化层电荷数 ( Qinj)的幂函数表达 .最后给出了基于 Idsat退化的寿命预测模型     

深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOI GCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.     

深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOIGCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.     

Constant Bias Stress Effects on Threshold Voltage of Pentacene Thin-Film Transistors Employing Polyvinylphenol Gate Dielectric

We investigate the stability of pentacene thin-film transistors using a poly(4-vinylphenol) (PVP) gate dielectric under constant bias stress. The threshold voltage is shifted to the positive gate voltage when stressed in air, as caused by water vapors in the PVP gate dielectric. Meanwhile, we observe a negative shift under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration 4.5 x 10¹¹ cm^-2 that is needed to avoid the critical degradation, resulting in a W/L larger than 40.     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

氮化镓基高电子迁移率晶体管Kink效应研究

研究了氮化镓(GaN)基高电子迁移率晶体管(HEMT)发生Kink效应的物理机制,并进行了实验测试。测试结果表明,当第一次扫描、漏极电压较大时,扩散进入耗尽区的电子在高场作用下形成热电子,碰撞电离出深能级施主态中的非平衡电子,第二次扫描的Kink效应减弱。当第一次扫描、漏极电压较小时,扩散进入耗尽区的电子被浅能级缺陷态捕获,第二次扫描的Kink效应增强。在开态下,增大反向栅极电压,可减小沟道电子浓度,进而减小电子捕获效应,Kink效应减弱。在半开态和闭态下,Kink效应不显著。最终得出,GaN缓冲层内类施主型缺陷态对沟道电子的捕获和热电子辅助去捕获,是Kink效应发生的主要原因。     

薄栅介质陷阱密度的求解和相关参数的提取

采用恒定电流应力对薄栅氧化层MOS电容进行了TDDB评价实验,提出了精确测量和表征陷阱密度及累积失效率的方法.该方法根据电荷陷落的动态平衡方程,测量恒流应力下MOS电容的栅电压变化曲线和应力前后的高频C-V曲线变化求解陷阱密度.从实验中可以直接提取表征陷阱的动态参数.在此基础上,可以对器件的累积失效率进行精确的评估.     

Effects of grain boundaries, field-dependent mobility, and interface trap States on the electrical Characteristics of pentacene TFT

We have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results. We have set up a model considering the polycrystalline nature of pentacene and the presence of grains and grain boundaries. We show how this model can be applied to different devices with different grain sizes and we analyze the relationship between mobility, grain size and applied gate voltage. On the basis of the simulation results, we can introduce an effective carrier mobility, which accounts for grain-related effects. The comparison between experimental results and simulations allows us to clearly understand the differences in the mobility derived by the analysis of current-voltage curve (as done experimentally by using standard MOSFET theory) and the intrinsic mobility of the organic layer. The effect of the pentacene/oxide interface traps and fixed surface charges has also been considered. The dependence of the threshold voltage on the density and energy level of the trap states has been outlined.     

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.     

Theory and experiments on surface 1/f noise

A theoretical low-frequency noise model for the epitaxial-channel surface field-effect structure is presented where random modulation of the channel conductance arises from fluctuation of charges trapped at the oxide trap states near the Si-SiO2interface. In this model, charge fluctuation in the oxide traps arises from carrier tunneling between the fast interface surface states and the oxide trap states. A second fluctuation, at higher frequencies, arises from the random thermal emission and capture of electrons and holes at the fast interface states through the thermal or Shockley-Read-Hall process. Different oxide trap densities were introduced into the interface region of the metal-oxide-silicon field-effect structures using a carefully controlled and reproducible oxygen heat treatment technique. Energy distributions of the oxide trap densities are obtained from capacitance measurements. Humps are observed between the flat band and the onset of strong surface inversion (lower half of the bandgap) in both the noise power and the oxide trap density versus gate voltage (or surface band bending) plots. Theoretical noise power calculations using the experimental oxide trap density profile from the capacitance-voltage data agree very well with the experimental noise humps in both magnitudes and fine structures. It is shown that the frequency spectra of noise depend strongly on the oxide trap density profile in the oxide. It is suggested that the oxide traps are due to the excess oxygen at the SiO2-Si interface.     

Charge trapping in ultrathin hafnium silicate/metal gate stacks

Charge trapping characteristics of MOCVD HfSi/sub x/O/sub y/ (20% SiO/sub 2/) gate stack of n-MOSFETs during substrate injection have been investigated. Positive constant voltage stress (CVS) and constant current stress (CCS) were applied at the gate of TiN-HfSi/sub x/O/sub y/-SiO/sub 2//p-Si n-MOSFETs having EOT of 2 nm. Significant electron trapping is observed from the positive shift of threshold voltage (/spl Delta/V/sub t/) after stress. Curve fitting of the threshold voltage shift data confirms power law dependence for Hf-silicate gate stacks. Charge pumping measurements for both cases showed significant electron trapping at bulk Hf-silicate while interface trap generation was comparatively insignificant. A turn-around effect is noticed for /spl Delta/V/sub t/ as the stress current and voltage increases under CCS and CVS. Dependence of spatial distribution of charge trapping at shallow traps on stress level in the Hf-silicate film and redistribution of trapped charges during and after removal of stress is possibly responsible for the turn-around effect.     

Effect of localized traps on the anomalous behavior of the transconductance in nanocrystalline TFTs

It has been reported that nanocrystalline and microcrystalline devices show an anomalous behavior in the transconductance where several rates of increase of the transconductance with applied gate voltage, not present in amorphous TFTs are observed. In this paper we show that the anomalous effect of the transconductance is observed for an acceptor tail states activation energy similar to the normal values for hydrogenated silicon amorphous devices, (a-Si:H), provided that some conditions are met regarding the density of trapped charge in tail and deep states and the density of free charge in the material, which does not necessarily suggest a behavior in between amorphous and polycrystalline. The effect appears if the density of deep tail states, is smaller (higher) than the typical values in a-Si:H. The localized state distribution present in a nanocrystalline TFT prepared by hot wire deposition technique is estimated by comparison of experimental and simulated transconductance curves. In our case a lower density of deep states is obtained, which corresponds with their better light and bias stability.     

Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al₂O₃ gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm²/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric.