Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio.     

Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor

Addition is the most primitive arithmetic operation in digital computation. Other arithmetic operations such as subtraction, multiplication, and division can all be performed by addition together with some logic operations. With the binary number system, addition speed is inevitably limited by the carry-propagation schemes. On the other hand, carry-free addition is possible when the modified signed-digit (MSD) number representation is used. We propose a novel optoelectronic scheme to handle the parallel MSD addition and subtraction operations. An optoelectronic shared content-addressable memroy is introduced. The shared content-addressable memory uses free-space optical processing to handle the large amount of parallel memory access operations and uses electronics to postprocess and derive logic decisions. We analyze the accuracy that the required optical hardware can deliver by using a statistical cross-talk-rate model that we propose. We also evaluate other important device and system performanceparameters, such as the memory capacity or the maximum number of parallel bits the adder can handle in terms of a given cross-talk rate at a certain repetition rate, the corresponding diffraction-limited memory density, and the system's power efficiency. To confirm the underlining operational principles of the proposed optoelectronic shared content-addressable-memory MSD adder, we design and perform initial experiments for handling 8-bit MSD number addition and subtraction and present the results.     

All-optical method for the addition of binary data by nonlinear materials

An all-optical system for the addition of binary numbers is proposed in which input binary digits are encoded by appropriate cells in two different planes and output binary digits are expressed as the presence (=1) or the absence (=0) of a light signal. The intensity-based optical XOR and AND logic operations are used here as basic building blocks. Nonlinear materials, appropriate cells (pixels), and other conventional optics are utilized in this system.     

Advanced all-optical logic gates on a spectral bus

We present experimental results on a new method for ultrafast all-optical logic, which utilizes four-wave mixing on polarization-modulated signals. The technique allows advanced operations such as exclusive-or and three-bit addition with carry bit. Furthermore, we show that on-the-fly error-correction encoding and decoding of a simple Hamming code is achieved when these gates are used on the bits of a spectrally structured word. These gates may be suitable for logic operations in an optoelectronic front end, which moves some of the necessary computation of data to the optical domain, before detection.     

A scheme of developing frequency encoded tristate-optical logic operations using semiconductor optical amplifier

The ever increasing demand for very fast and agile optical networks requires very fast execution of different optical and logical operations as well as large information handling capacities at the same time. In conventional binary logic based operations the information is represented by two distinct states only (0 and 1 state). It limits the large information handling capacity and speed of different arithmetic and optical logic operations. Tristate based logic operations can be accommodated with optics successfully in data processing, as this type of operation can enhance the speed of operation as well as increase the information handling capacity. Here in this communication the author proposes a new method to implement all-optical different logic gates with tristate logic using the frequency-encoding principle. The frequency encoding/decoding based optical communication has distinctly great advantages because the frequency is the fundamental character of an optical signal and it preserves its identity throughout the communication. The principle of the rotation of the state of polarization of a probe beam through semiconductor optical amplifier (SOA), frequency routing property of an optical add/drop multiplexer (AD) and high frequency conversion property of reflecting semiconductor optical amplifiers (RSOA) have been exploited here to implement the desired AND, OR, NAND and NOR logic operations with tristate logic.     

Digital Processing and Communication with Molecular Switches

The tremendous pace in the development of information technology is rapidly approaching a limit. Alternative materials and operating principles for the elaboration and communication of data in electronic circuits and optical networks must be identified. Organic molecules are promising candidates for the realization of future digital processors. Their attractive features are the miniaturized dimensions and the high degree of control on molecular design possible in chemical synthesis. Indeed, nanostructures with engineered properties and specific functions can be assembled relying on the power of organic synthesis. In particular, certain molecules can be designed to switch from one state to another, when addressed with chemical, electrical, or optical stimulations, and to produce a detectable signal in response to these transformations. Binary data can be encoded on the input stimulations and output signals employing logic conventions and assumptions similar to those ruling digital electronics. Thus, binary inputs can be transduced into binary outputs relying on molecular switches. Following these design principles, the three basic logic operations (AND, NOT, and OR) and more complex logic functions (EOR, INH, NOR, XNOR, and XOR) have been reproduced already at the molecular level. Presently, these simple “molecular processors” are far from any practical application. However, these encouraging results demonstrate already that chemical systems can process binary data with designed logic protocols. Further fundamental studies on the various facets of this emerging area will reveal if and how molecular switches can become the basic components of future logic devices. After all, chemical computers are available already. We all carry one in our head!     

Logic Computing with Stateful Neural Networks of Resistive Switches

Brain‐inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal–oxide–semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two‐input logic operations with just one step, except for the exclusive‐OR (XOR) needing two sequential steps. 1‐bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.     

Optoelectronic butterfly interconnection architecture of modified signed-digit arithmetic systems: fully parallel adder and subtracter

The carry-free property of modified signed-digit addition is discussed, and a space-position-logic-encoding scheme is proposed, which not only makes best use of the convenience of binary (0, 1) logic operation but is also suitable for the trinary (1, 0, 1-) property of modified signed-digit digits. Based on the spaceposition-logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch modules and butterfly interconnections; thus an effective combination of a parallel algorithm and a parallel architecture is implemented. The effectiveness of this architecture is verified by both simulation and experimental results.     

Programmable DNA Nanoindicator‐Based Platform for Large‐Scale Square Root Logic Biocomputing

The prospect of programming molecular computing systems to realize complex autonomous tasks has advanced the design of synthetic biochemical logic circuits. One way to implement digital and analog integrated circuits is to use noncovalent hybridization and strand displacement reactions in cell‐free and enzyme‐free nucleic acid systems. To date, DNA‐based circuits involving tens of logic gates capable of implementing basic and complex logic functions have been demonstrated experimentally. However, most of these circuits are still incapable of realizing complex mathematical operations, such as square root logic operations, which can only be carried out with 4 bit binary numbers. A high‐capacity DNA biocomputing system is demonstrated through the development of a 10 bit square root logic circuit. It can calculate the square root of a 10 bit binary number (within the decimal integer 900) by designing DNA sequences and programming DNA strand displacement reactions. The input signals are optimized through the output feedback to improve performance in more complex logical operations. This study provides a more universal approach for applications in biotechnology and bioengineering.     

All-optical arithmetic unit with the help of terahertz-optical-asymmetric-demultiplexer-based tree architecture

An all-optical arithmetic unit with the help of terahertz-optical-asymmetric-demultiplexer (TOAD)-based tree architecture is proposed. We describe the all-optical arithmetic unit by using a set of all-optical multiplexer, all-optical full-adder, and optical switch. The all-optical arithmetic unit can be used to perform a fast central processor unit using optical hardware components. We have tried to exploit the advantages of both optical tree architecture and TOAD-based switch to design an integrated all-optical circuit that can perform binary addition, addition with carry, subtract with borrow, subtract (2's complement), double, increment, decrement, and transfer operations.     

Optical programmable Boolean logic unit

Logic units are the building blocks of many important computational operations likes arithmetic, multiplexer-demultiplexer, radix conversion, parity checker cum generator, etc. Multifunctional logic operation is very much essential in this respect. Here a programmable Boolean logic unit is proposed that can perform 16 Boolean logical operations from a single optical input according to the programming input without changing the circuit design. This circuit has two outputs. One output is complementary to the other. Hence no loss of data can occur. The circuit is basically designed by a 2×2 polarization independent optical cross bar switch. Performance of the proposed circuit has been achieved by doing numerical simulations. The binary logical states (0,1) are represented by the absence of light (null) and presence of light, respectively.     

Modeling of large plastic deformation behavior and anisotropy evolution in cold rolled bcc steels using the viscoplastic ?-model-based grain-interaction

In this paper, a micromechanical approach is used to predict the mechanical response and anisotropy evolution in BCC metals. Particularly, cold rolling textures and the corresponding yield surfaces are simulated using the newly developed viscoplastic intermediate ?-model. This model takes into account the grain interactions but without the Eshelby theory. In this work, we compare our results to those predicted by the upper and lower bounds (Taylor and Static) as well as those of the viscoplastic self-consistent (VPSC) model. The results are compared in terms of predicted slip activity, texture evolution and yield loci. For the simulations, we considered two cases: the restricted slip, {1 1 0}〈1 1 1〉, and the pencil glide, {1 1 0}〈1 1 1〉 + {1 1 2}〈1 1 1〉 + {1 2 3}〈1 1 1〉. In addition, we present a qualitative comparison with experimental cold rolling textures taken from the literature for several BCC metals: electrical, ferritic, Interstitial-Free (IF) and low carbon steels. Our results show that the pencil glide assumption is adequate for low carbon and IF-steels and that the restricted slip assumption is well suited for ferritic and electrical steels.     

微光成象系统中实时降噪的优化设计

微光电视工作于极低照度或恶劣环境下，输出信噪比明显降低，目标完全淹没在背景噪声中，使探测率大大下降。提出了用帧间处理技术消除加性噪声。论述了字长和滤波系数的选择原则。研究了实时去噪的几项关键技术，算法和符号位的设计，各部分工作时间分配以及大背景噪声下时种同步方法。     

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.     

All-optical quaternary logic gates

Conventional binary logic based operations restrict the speed of operations as well as information handling capacity. A way to overcome these limitations is the implementation of multivalued logic operations in the optical domain. Multivalued logic operations not only enhance the data handling capacities but also increase the speed of processing. integrating enormous potential bandwidth of optical fiber as information carrying medium and faster optoelectronic/optical switches with no hardware complexity. A new method is proposed for the implementation of all-optical quaternary inversion, MAX, MIN, and equality operations using frequency-encoded data. Cross phase modulation-based frequency conversion, polarization switch (PSW) characteristics of a semiconductor optical amplifier (SOA), frequency routing by a wave division multiplexer (MUX), and a demultiplexer (DMUX) have been exploited to implement the desired quaternary logic operations. Simulation results support the feasibility of the proposed scheme.     

Extended coding for optical array logic

We present extended coding for optical array logic (OAL) to avoid the marginal effect. The marginal effect is defined as an effect caused by the finite size of the image region, and it is a problem in massively parallel processing by OAL. OAL is a paradigm of optical computing suitable for optical implementation utilizing image coding and discrete correlation. To avoid the marginal effect in the context of OAL, we propose a new coding rule and consider possible operations with this coding. With extended coding, binary data can be identified from background with the same number of pixels as that used in the original OAL. Simulation results of the operations verify the correctness of the proposed technique.     

Enhanced geometrical superresolved imaging with moving binary random mask

In this paper, we address the geometrical resolution limitation of an imaging sensor caused by the size of its pixels yielding insufficient spatial sampling of the image. The spatial blurring that is caused due to inadequate sampling can be resolved by placing a two-dimensional binary random mask in an intermediate image plane and shifting it along one direction while keeping the sensor as well as all other optical components fixed. Out of the set of images that are captured, a high resolution image can be decoded. In addition, this approach allows improved robustness to spatial noise.     

Adiabatic pipelining: a key to ternary computing with quantum dots

The quantum-dot cellular automaton (QCA), a processing platform based on interacting quantum dots, was introduced by Lent in the mid-1990s. What followed was an exhilarating period with the development of the line, the functionally complete set of logic functions, as well as more complex processing structures, however all in the realm of binary logic. Regardless of these achievements, it has to be acknowledged that the use of binary logic is in computing systems mainly the end result of the technological limitations, which the designers had to cope with in the early days of their design. The first advancement of QCAs to multi-valued (ternary) processing was performed by Lebar Bajec et al, with the argument that processing platforms of the future should not disregard the clear advantages of multi-valued logic. Some of the elementary ternary QCAs, necessary for the construction of more complex processing entities, however, lead to a remarkable increase in size when compared to their binary counterparts. This somewhat negates the advantages gained by entering the ternary computing domain. As it turned out, even the binary QCA had its initial hiccups, which have been solved by the introduction of adiabatic switching and the application of adiabatic pipeline approaches. We present here a study that introduces adiabatic switching into the ternary QCA and employs the adiabatic pipeline approach to successfully solve the issues of elementary ternary QCAs. What is more, the ternary QCAs presented here are sizewise comparable to binary QCAs. This in our view might serve towards their faster adoption.     

Simple,fast, label-free,and nanoquencher-free system for operating multivalued DNA logic gates using polythymine templated CuNPs as signal reporters

Boolean logic devices play a key role in both traditional and nontraditional molecular logic circuits.This kind of binary logic,in which each bit is coded by (0,1),has only two output states—on or off (or high/low).Because of the finite computing capacity and variation,it is facing challenges from multivalued logic gates while processing high-density or uncertain/imprecise information.However,a low-cost,simple,and universal system that can perform different multivalued logic computations has not yet been developed,and remains a concept for further study.Herein,taking the ternary OR and INHIBIT logic gates as model devices,we present the fabrication of a novel simple,fast,label-free,and nanoquencher-free system for multivalued DNA logic gates using poly-thymine (T) templated copper nanoparticles (CuNPs) as signal reporters.The mixture of Cu2+ and ascorbic acid (AA) is taken as a universal platform for all ternary logic gates.Different kinds of poly-T strands and delicately designed complementary poly-adenine (A) strands are alternatively applied as ternary inputs to exhibit the ternary output states (low/0,medium/1,high/2).Notably,there are no nanoquenchers in this platform as poly-A strands can function as not only inputs but also efficient inhibitors of poly-T templated CuNPs.Moreover,all DNA are unlabeled single-strand DNA that do not need sophisticated labeling procedures or sequence design.The above design greatly reduces the operating time,costs,and complexity.More importantly,the ternary logic computations can be completed within 20 min because of the fast formation of CuNPs,and all of them share the same threshold values.     

Quantum network architecture of tight-binding models with substitution sequences

Abstract

We study a two-spin quantum Turing architecture, in which discrete local rotations {α_m} of the Turing head spin alternate with quantum controlled NOT operations. Substitution sequences are known to underlie aperiodic structures. We show that parameter inputs {α_m} described by such sequences can lead here to a quantum dynamics, intermediate between the regular and the chaotic variant. Exponential parameter sensitivity characterizing chaotic quantum Turing machines turns out to be an adequate criterion for induced quantum chaos in a quantum network.