高性能低存储的2维离散小波变换架构

针对JPEG2000中的5/3小波和9/7小波存在的高存储问题,通过改进离散小波变换(DWT)的提升算法,提出了一种统一的高性能、低存储的2维离散小波变换架构.采用该算法实现的2维离散小波变换架构不仅省去了行列模块间的转置缓存,而且减小了片内缓存的大小.对于N×N大小的图像(N为图像宽度)进行5/32维DWT仅需要2N大小的片内缓存,进行9/7 2维DWT仅需要4N大小的片内缓存,而且通过采用流水线技术还可将关键路径缩短为一个乘法器的延时.和已有的2维DWT架构相比,该统一架构具有更低的片内存储器需求和更高的性能.该架构经Verilog HDL描述,并在ModelSim中验证正确.在Ahera Stratix Ⅱ FPGA EP2S60F1024C4中综合的结果显示,对于1 024×1 024大小的图像,需要1 284个ALUT,片内存储器的大小为4 K,最高频率可达172.56 MHz.     

基于改进粒子群优化算法的二维静态离散小波图像去噪研究

提出了一种结合改进的粒子群优化算法及二维静态离散小波变换实现图像去噪的方法.由于图像在离散小波变换(discrete wavelet transform,DWT)处理下,经过低通、高通滤波器的卷积后,丢失了其中奇数项所含的时移信息,为了更好的满足时间不变性,可以采用二维静态离散小波变换实现图像的分解,然后将改进的粒子群优化算法应用于图像小波阈值去噪.对比实验结果表明,该方法的增强图像效果和去噪性能明显优于传统的小波阈值去噪.     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。     

二维离散小波变换高效低存储VLSI架构设计*

通过改进二维离散小波变换(2D DWT)的提升算法,提出一种高效的硬件架构,可省去行列模块间的转置缓存,减少片内存储器需求,并可利用同一2D DWT架构实现JPEG 2000中的5/3和9/7 变换。对于N×N的图像（N为图像宽度）,进行5/3 变换仅需2N片内缓存,进行9/7变换仅需4N片内缓存,关键路径为一个乘法器的延时。与已有的2D DWT架构相比,本架构省去了行列模块间的转置缓存,并利用折叠技术和流水线技术降低了硬件开销,缩短了关键路径,有效提升了系统性能。     

基于DCT的时序数据相似性搜索

数据的高维度是造成时序数据相似性搜索困难的主要原因。最有效的解决方法是对时序数据进行维归约，然后对压缩后的数据建立空间索引。目前维归约的方法主要是离散傅立叶变换(DFT)和离散小波变换(DWT)。提出了一种新的方法，利用离散余弦变换(DCT)进行维归约，并在此基础上给出了对时序数据进行范围查询和近邻查询的相似性搜索方法。与基于DFT、DWT的搜索方法相比，该方法在理论分析和实验结果上都显示出较高的效率。     

一种基于感知成型及矩傅立叶矩阵描述子的鲁棒性数字水印方案

提出了一种结合离散小波变换（DWT）,离散余弦变换（DCT）,感知模型（HVS）及矩傅立叶矩阵描述子（MFMD）的图像数字水印方案。该方法把原始图像进行二维DWT分解,保留其高频细节部分,然后对小波逼近子图进行二维DCT变换并结合HVS进行水印嵌入。水印的检测则采用了相关性与MFMD相结合的方法。实验结果表明该水印方案很好地实现了水印系统所要求的基本特性,诸如嵌入有效性,保真度,数据有效载荷及鲁棒性等等。     

提升小波变换的三种算法性能比较

离散小波变换(DWT)在语音,图像等信号处理中有着广泛的应用,在JPEG2000标准中就推荐采用5/3和9/7小波来分别进行无损和有损图像压缩,取代基于DCT变换的图像压缩,并且还推荐采用提升方法来实现。提出三种基于提升方法的二维离散小波变换的并行算法,并在超常超标量数字指令(VLIW)的数字信号处理器(DSP)上进行了性能方面的比较。这里,我们以在图像压缩中常用的不同分辨率的图像作为实验对象。实验结果表明,此三种算法对图像数据进行小波变换的处理时间有了明显缩短,并且实现在参数空间的不同点上都得到更好的效果。     

基于提升算法JPEG2000小波变换的硬件实现

提出了一种基于提升算法的高效JPEG2000二维离散小波变换(2D-DWT)硬件结构,将边界延拓内嵌于离散小波变换过程中,减少了所需的内存空间和功耗。采用W扫描输入方式和行列并行处理结构,加快了变换速度,大大提高了小波变换的效率。整个二维离散小波变换结构已经通过FPGA硬件仿真验证。     

基于FPGA的二维提升小波变换IP核设计

提出了一种高效并行的二维离散提升小波(DWT)变换结构,该结构只需要7行教据缓存,即可实现行和列方向同时进行滤波变换.采用一种基于CSD编码和优化的移位加操作实现常系数乘法器,整个小波变换插入多级流水线寄存器,加快了处理速度.用VHDL设计可自动验证的testbench,通过matlab+modelsim联合仿真能方便有效地对IP核进行验证.此IP核具有3个可配置参数,分别为图像尺寸、位宽、小波变换的级数,可方便重用.该IP核已经在XC2VP20 FPGA上实现,并能稳定工作在60MHz时钟频率下,其处理512512 8bil图像的速度可达240帧/s,完全能满足高速图像实时处理要求.     

基于级联离散小波变换的信号去噪方法研究

提出了基于级联离散小波变换的信号去噪方法。该方法通过对带噪信号作一层离散小波变换(DWT)后提取的低频部分和高频部分分别作一层DWT和四层DWT,然后,对低频部分提取的低频成分和高频成分均作三层DWT,接着,对所有分解的小波系数进行阈值处理,最后,完成信号重构。实验结果表明:在同样的小波分解层次下,本方法去噪效果好于DWT法和WPD法。     

多值图像连通域标记ASIC结构设计

提出了一种能够实时实现多值图像连通域标记算法的ASIC系统结构.该器件采用基于像素的图像连通域标记算法,通过分析存储器需求,减少了片内存储器容量,以及存储器访问所需要的时钟周期数,使图像标记的总时钟数降为N×M×4,N为图像行数,M为列数.仿真结果表明,ASIC能够满足大部分实时目标识别系统的要求.     

一种高效的CABAC解码器硬件结构设计

相对于其他熵编码而言,基于上下文的自适应二进制算术熵编码（CABAC）具有更大的数据压缩率,但由于其运算复杂,访问存储设备频繁,导致编／解码率较低。针对影响CABAC解码速度的“瓶颈”问题,提出了一种高效的CABAC解码器硬件结构,包括新的存储访问方式、优化的解码核心单元结构以及子解码器级联的方式。实验结果表明,该硬件结构可显著提高CABAC的解码效率。     

A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme

In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform （DWT） using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.     

Cache-only memory architectures

The shared memory concept makes it easier to write parallel programs, but tuning the application to reduce the impact of frequent long latency memory accesses still requires substantial programmer effort. Researchers have proposed using compilers, operating systems, or architectures to improve performance by allocating data close to the processors that use it. The Cache-Only Memory Architecture (COMA) increases the chances of data being available locally because the hardware transparently replicates the data and migrates it to the memory module of the node that is currently accessing it. Each memory module acts as a huge cache memory in which each block has a tag with the address and the state. The authors explain the functionality, architecture, performance, and complexity of COMA systems. They also outline different COMA designs, compare COMA to traditional nonuniform memory access (NUMA) systems, and describe proposed improvements in NUMA systems that target the same performance obstacles as COMA     

基于FPGA的高性能离散小波变换设计

针对db8(Daubechies 8)小波设计了高速正、反变换系统,用DE2开发板进行了系统验证。正、反变换的最高时钟频率分别达到217.72 MHz和217.58 MHz。对比同类文献中的设计,本设计在最高处理速度方面具有明显优势。基于此,考虑通用性,还设计了一种通用小波变换FPGA架构。该架构通用性强,可高性能实现多种小波变换。采用DA算法、LUT结构、流水线技术等对设计进行了优化。     

Data compression techniques in Wireless Sensor Networks

The advancement in the wireless technologies and digital integrated circuits led to the development of Wireless Sensor Networks (WSN). WSN consists of various sensor nodes and relays capable of computing, sensing, and communicating wirelessly. Nodes in WSNs have very limited resources such as memory, energy and processing capabilities. Many image compression techniques have been proposed to address these limitations; however, most of them are not applicable on sensor nodes due to memory limitation, energy consumption and processing speed. To overcome this problem, we have selected Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) image compression techniques as they can be implemented on sensor nodes. Both DCT and DWT allow an efficient trade-off between compression ratio and energy consumption. In this paper, both DCT and DWT are analyzed and implemented using TinyOS on TelosB hardware platform. The metrics used for performance evaluation are peak signal-to-noise ratio (PSNR), compression ratio (CR), throughput, end-to-end (ETE) delay and battery lifetime. Moreover, we also evaluated DCT and DWT in a single-hop and in multi-hop networks. Experimental results show that DWT outperforms DCT in terms of PSNR, throughput, ETE delay and battery lifetime. However, DCT provides better compression ratio than DWT. The average media access control layer (MAC) delay for both DCT and DWT is also calculated and experimentally demonstrated.     

Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video

This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.     

基于DRAM和PCM的混合主存模拟器

相变存储器（PCM）由于其非易失性、高读取速度以及低静态功耗等优点,已成为主存研究领域的热点.然而,目前缺乏可用的PCM设备,这使得基于PCM的算法研究得不到有效验证.因此,本文提出了利用主存模拟器仿真并验证PCM算法的思路.本文首先介绍了现有主存模拟器的特点,并指出其并不能完全满足当前主存研究的实际需求,在此基础上提出并构建了一个基于DRAM和PCM的混合主存模拟器.与现有模拟器的实验比较结果表明,本文设计的混合主存模拟器能够有效地模拟DRAM和PCM混合存储架构,并能够支持不同形式的混合主存系统模拟,具有高可配置性.最后,论文通过一个使用示例说明了混合主存模拟器编程接口的易用性.     

Orthogonal multiprocessor sharing memory with an enhanced mesh for integrated image understanding

This paper proposes a new parallel architecture, which has the potential to support low-level image processing as well as intermediate and high-level vision analysis tasks efficiently. The integrated architecture consists of an SIMD mesh of processors enhanced with multiple broadcast buses, and MIMD multiprocessor with orthogonal access buses, and a two-dimensional shared memory array. Low-level image processing is performed on the mesh processor, while intermediate and high-level vision analysis is performed on the orthogonal multiprocessor. The interaction between the two levels is supported by a common shared memory. Concurrent computations and I/O are made possible by partitioning the memory into disjoint spaces so that each processor system can access a different memory space. To illustrate the power of such a two-level system, we present efficient parallel algorithms for a variety of problems from low-level image processing to high-level vision. Representative problems include matrix based computations, histogramming and key counting operations, image component labeling, pyramid computations, Hough transform, pattern clustering, and scene labeling. Through computational complexity analysis, we show that the integrated architecture meets the processing requirements of most image understanding tasks.