A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance     

Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256×16×128 to 2 K×16×256 (Word×Bit×Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations     

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 μm design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I_ccl) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application     

Design issues and insights for low-voltage high-density SOI DRAM

A physics-based study of floating-body effects on the operation of SOI DRAM is described. The study, which is based on device and circuit simulations using a physical SOI MOSFET model calibrated to an actual partially-depleted (PD) SOI DRAM technology, addresses the performance of the peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the data storage cell. Design insight for low-voltage high-density SOI DRAM is attained. Double cell design is shown to yield a dynamic retention time long enough for gigabit memories, and crude body-source ties for nMOS, with pMOS bodies floating, are shown to effectively suppress instabilities in the sense amplifier     

High-speed DRAM architecture development

This paper is an overview of the high-speed DRAM architecture developments. We discuss developments on density growth, interface technology, memory-core architecture, and DRAM+ASIC technology. We can find the developments of density as 2× growth instead of 4× by each generation. Interface technologies will have a tendency to use the terminated bus structure for higher data rate. Memory-core architecture developments are the trials for actual bandwidth improvements. DRAM+ASIC technologies seem to require universal interface solutions. We tried to show that no single solution is able to cover the wide diversity of future system requirements     

High-performance sub-quarter-micrometer PMOSFET's on SOI

PMOS transistors with effective channel lengths down to 0.15 μm have been fabricated on silicon-on-insulator (SOI) films. Gate oxide thicknesses of 5.5 and 10 nm are used. These P⁺ gate PMOS devices exhibit excellent short-channel behavior, low-source-drain resistance, and remarkably large current drive and transconductance. for T_ox=5.5 nm, saturation transconductances of 274 mS/mm at 300 K and 352 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. The result is attributed to low series resistance, forward-bias body effect, and the reduction of body charge effect     

High-performance fully-depleted SOI RF CMOS

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f _max is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-μm gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement and a 0.3~1.8-V larger word-line voltage margin to write ONE data into the cell     

嵌入式系统中存储器性能研究

动态随机存储器是嵌入式系统的一个重要组成部分,而动态随机存储器故障是嵌入式系统故障的一个主要原因之一。在此从动态随机存储器的结构和失效模型出发,有针对地提出了用于检测性能的数据和读写方式,实验证明通过提出的检测方法能够有效地找出潜在的存储器故障,从而能够为嵌入式系统设计人员提供改善系统性能的方法和途径。     

High-performance VLSI architecture for the Viterbi algorithm

The Viterbi (1967) algorithm (VA) is known to be an efficient method for the realization of maximum-likelihood (ML) decoding of convolutional codes. The VA is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. We present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated, optimizing the use of the PEs and the communications. Therefore, the algorithm is mapped onto a column of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints. Furthermore, the management of the surviving path memory for its mapping and distribution among the processors was studied. As a result, we obtain a regular and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data recirculations between stages     

Partial SOI type isolation for improvement of DRAM cell transistor characteristics

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

Design methodology of embedded DRAM with virtual-socketarchitecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-μm design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT     

Dynamic data retention and implied design criteria forfloating-body SOI DRAM

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications     

Measurement of transient effects in SOI DRAM/SRAM accesstransistors

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V_DD for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

高性能交通标志检测模块的VLSI结构设计

交通标志检测是驾驶辅助系统的重要功能,但对实时性极高的要求使其非常具有挑战性。提出了一种高性能禁令标志检测模块的VLSI结构,并在FPGA平台上完成了实现和验证。该结构的基本原理是同时利用颜色与形状特征,在图像的红色边缘位图中采用圆霍夫变换检测圆形。通过挖掘圆霍夫变换的局部特性,所提出的结构在内存占用方面显著低于常规结构。所有半径同时投票的设计使FPGA的逻辑单元和内存的并行性得以充分发挥。该结构在Altera公司的EP3C55F484C6型FPGA上进行了验证,其最大可运行频率达到122 MHz,且资源占用在可接受范围内。实验结果表明:该结构的吞吐量达到115 M像素/s,且对低光照条件、局部遮挡、多标志相连和相似背景颜色等不利条件具有良好的适应能力。     

Compact wide bandwidth dual-port DRAM architecture suitable for mobile multimedia processors

A DRAM architecture capable of providing dual-port interface is presented. The architecture utilises a novel global bitline scheme to obtain a very wide data bandwidth not possible using traditional DRAM architectures. Furthermore, the area penalty is minimised by using a conventional one-transistor one-capacitor cell coupled with special sensing units that have 84.6% more transistor count. The architecture allows simultaneous read and write access using a conventional two-metal DRAM fabrication process.     

Power-efficient flexible processor architecture for embedded applications

In the design of embedded systems, a processor architecture is a tradeoff between energy consumption, area, speed, design time, and flexibility to cope with future design changes. New versions in a product generation may require small design changes in any part of the design. We propose a novel processor architecture concept, which provides the flexibility needed in practice at a reduced power and performance cost compared to a fully programmable processor. The crucial element is a novel protocol combining an efficient, customized component with a flexible processor into a hybrid architecture.