A versatile ECL multiplexer IC for the Gbit/s range

A new approach to digital multiplexing for communication systems operating in the Gbit/s range is presented. With a single function, monolithically integrated in the established silicon bipolar process, many operations required by the communication system's multiplex equipment are achieved at data rates of up to 3 Gbits/s. The IC is a four-channel multiplexer designed to interface readily with ECL families. Demonstrations of the ICs performance include pseudorandom pattern generation by multiplexing ECL inputs up to 2 Gbits/s, demultiplexing into ECL registers at 1 Gbits/s, clock extraction in a 560 Mbit/s coaxial cable transmission system, and a modulo-n divider technique for timing generation using ECL feedback shift registers for frequencies up to 1.6 GHz. The demonstrations highlight the multiplexer's ability to effectively extend the system speed limit of commercially available ECL from a few hundred Mbits/s to the Gbit/s range. An eight-input multiplexer using three chips in a hybrid assembly is demonstrated multiplexing a static input pattern up to 2.8 Gbits/s.     

New data regeneration scheme for multi-Gbit/s fibre-optic links

A novel optical regeneration scheme without using nonlinear clock recovery elements has been demonstrated in a transmission experiment at 2.4 Gbit/s over 35 km of fibre. In this scheme, the clock is superimposed on the data signal at the transmitter end, and is separated from the composite signal by passive filters at the receiver end for data regeneration     

16 Gbit/s multiplexer experiment

A multiplexer experiment was performed that provided an n.r.z.-format serial-output pulse stream of 16 Gbit/s bit rate and 2 V across a load of 50 ?. The bit rate of the input tributaries was 1.12 Gbit/s. The multiplexer circuit essentially employed ultrabroadband hybrid tees, fast step-recovery diodes, and fast GaAs Schottky-barrier diodes.     

A microwave injection-locking technique for direct timingextraction in multi-Gbit/s fiber optic data links

Direct timing extraction up to 5.8 GHz in a modified-Manchester-coded time-division multiplexed (TDM) fiber-optic transmission system is reported. The presence of an enhanced discrete timing component surrounded by depressed continuous components in the spectra of the received data is demonstrated experimentally and is supported by theory. The enhanced discrete component is used to injection-lock an electronic oscillator, thus directly generating a large timing signal. The technique is suitable for direct optical injection-locking for timing extraction     

2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design     

Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.     

2.5Gb/sGaAs激光器高速驱动电路

研制出一种实用化的ＧａＡｓ激光器高速驱动电路,该电路采用源耦合场效应管逻辑电路形式,０．８μｍ栅工艺,全离子注入平面工艺,单电源（－５．２Ｖ）供电。并给出了研究结果：最大驱动电流可达４５ｍＡ,数据传输速率２．５Ｇｂ／ｓ。     

具有时钟提取及倍频功能的 5Gb/s全速率复接器设计

采用SMIC 0．18μm CMOS工艺设计了一个具有时钟提取及倍频功能的5Gb／s全速率2：1复接电路。整个电路由两部分构成,即：全速率2：1复接器和时钟提取及倍频环路。其中,后者从一路2．5Gb／S输入数据中提取出时钟信号,并为前者提供所需的2．5GHz及5GHz的时钟。Pottbgcker鉴频鉴相器被运用以提高环路的捕获带宽。设计广泛采用了具有速度高和抗干扰能力强等诸多优点的电流模逻辑。仿真结果表明,本电路无需任何参考时钟,无需外接元件及手动相位调整或辅助捕获,就能可靠地工作在2．4～2．9Gb／s的输入数据速率上。芯片面积为812μm×675μm。电源电压1．8V时,功耗为162mW。     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.     

50 Gbit/s 2:1 multiplexer in 0.13 /spl mu/m CMOS technology

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 /spl Omega/ load. The IC is fabricated in a 0.13 /spl mu/m bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2/spl times/100 mV.     

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.     

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.     

基于0.13微米锗硅BiCMOS工艺的80 Gb/s 2:1 复接器

本文介绍了基于0.13微米锗硅BiCMOS工艺设计的超高速2:1复接器芯片,工艺fT为103 GHz。为了最大限度提高工作速度,系统方案进行了优化,采用了选择器输出直接驱动片外50 Ω负载的形式,并在输入级集成了两个宽带数据放大器和一个时钟放大器。经测试,芯片输出眼图达到了80 Gb/s的速率,单端电压摆幅为160 mV。     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

A 15-gb/s 2:1 multiplexer in 0.18-/spl mu/m CMOS

By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-/spl mu/m CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps.     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect andadd/drop multiplexer solution

This paper presents a single-chip all-CMOS solution for 4×OC-3c, OC-12, and OC-12c synchronous digital hierarchy/synchronous optical network (SDH/SONET) framing with integrated serial line interfaces. Outstanding features of this chip are clock and data recovery and fulfillment of ITU-T and Bellcore jitter requirements for SDH/SONET systems, as well as the large range of functions offered. These functions include asynchronous transfer mode (ATM) and point-to-point protocol (PPP) support, as well as built-in native SDH/SONET functions such as digital cross-connect, add/drop multiplexing, and automatic protection switching. In addition, the chip is based on a new scalable modular architecture     

40-Gb/s packet-selective photonic add/drop multiplexer based on optical-code label header processing

A packet-by-packet-selective photonic add/drop multiplexer, of the finest data granularity, is experimentally demonstrated at 40 Gb/s. An optical-code label, attached to the packet, enables determination, in the optical domain, of whether to drop, cut through, or add packets.     

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

A low-power 16:1 multiplexer (MUX) IC using undoped-emitter InP/InGaAs heterojunction bipolar transistors (HBTs) has been successfully designed and fabricated. To minimise power consumption, the collector current density of each HBT was optimised taking into account the required operating speed and the number of fan-outs. Up to 47 Gbit/s error-free operation was confirmed with low power consumption of about 3.2 W. These results demonstrate that InP/InGaAs HBT technology is attractive for fabricating over 40 Gbit/s, low-power medium-scale-integration (MSI) circuits.