16 Gbit/s multiplexer experiment

A multiplexer experiment was performed that provided an n.r.z.-format serial-output pulse stream of 16 Gbit/s bit rate and 2 V across a load of 50 ?. The bit rate of the input tributaries was 1.12 Gbit/s. The multiplexer circuit essentially employed ultrabroadband hybrid tees, fast step-recovery diodes, and fast GaAs Schottky-barrier diodes.     

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.     

High-bit-rate pulse regeneration and modulation of injection lasers with a planar Gunn device

A simple circuit with a Schottky-barrier-gate Gunn device is presented, which works as a pulse regenerator and modulator for laser diodes. Modulation depth and bias voltages of both Gunn device and laser are separately adjustable, allowing quick adaption for different laser diodes. The circuit was tested with a p.c.m. word at 1.5 Gbit/s.     

Monolithic integration of laser diodes, photomonitors, and laser driving and monitoring circuits on a semi-insulating GaAs

A monolithic optoelectronic-integrated circuit (OEIC) incorporating laser diodes, photomonitors, and laser driving and monitoring circuits has been fabricated on a semi-insulating GaAs substrate. The structure and circuit design considerations, the fabrication processes, and the static and dynamic characteristics of the device are described. The device has been successfully operated up to 2 Gbit/s.     

Simple integrated circuit with Gunn devices

This letter describes the structure and electrical performance of a simple integrated digital circuit on GaAs using Gunn devices, which is capable of operating at up to 2 Gbit/s. A directed transfer of domain pulses within the circuit, which is almost free of reactive effects, is achieved by employing Schottky-barrier diodes.     

CML-type MOnostable BIstable logic element (MOBILE) using InP-based monolithic RTD/HBT technology

A new CML-type monostable/bistable logic element IC is fabricated using monolithically integrated resonant tunnelling diodes (RTDs) and InP/InGaAs heterojunction bipolar transistors (HBTs). The D-flip-flop function of the fabricated circuit is confirmed up to 20 Gbit/s at room temperature. This result indicates the potential of the RTD/HBT technology for high-speed logic applications.     

Retiming circuit for n.r.z. signals in 1.12 Gbit/s optical transmission system

A circuit for retiming a 1.12 Gbit/s n.r.z. signal in an optical transmission system is described. Retiming in the repeater is accomplished by sampling the n.r.z. signal with a 1.12 GHz clock signal. The resulting r.z. signals are fed to a Schmitt trigger which acts as an RS flip-flop, where the r.z. signals are converted back to n.r.z. signals.     

Silicon bipolar decision circuit handling bit rates up to 5 Gbit/s

A high-speed silicon bipolar decision circuit is presented which operates up to 5 Gbit/s. It may serve as a subcomponent for integration in a regenerator/repeater circuit for multi-gigabit fiber-optic trunk lines. The circuit was implemented in a standard bipolar silicon technology featuring oxide-wall isolation, 2-μm emitter stripe widths, and a transit frequency of 9 GHZ atV_{CE} = 1V. The measured clock-phase-margin of the decision circuit at 4 Gbit/s corresponds to two thirds of a bit slot and to half a bit slot at 5 Gbit/s. The minimum input sensitivity at 4 Gbit/s is less than 150 mV.     

IP网中40 Gbit/s链路需求解决方案

本文阐述了IP网中40 Gbit/s链路需求的背景,介绍了40 Gbit/s关键技术,提出了IP网中40 Gbit/s链路应用解决方案.     

High performance 10-12.5 Gbit/s modulator driver in InP SHBT technology

A high performance modulator driver circuit is presented using 4" InP SHBT technology. The IC was developed for driving EAM modulators in OC-192 (10 Gbit/s) and with forward error correction (FEC: 10.7 Gbit/s or 12.5 Gbit/s) optical fibre systems. The monolithic integrated circuit features output amplitude control, output crossing point control and output DC offset control. Measured results show the circuit operates at 10 to 12.5 Gbit/s with a swing of 3.1 V/sub p-p/ at each output and 20/18 ps rise/fall times. The power dissipation is 1.4 W with a standard power supply of -5.2 V.     

Pulse Regeneration in the Gigabit-Per-Second Range Using a Diode Differential Regenerator

A clocked pulse regenerator circuit (diode differential regenerator (DDR)) is described which employs a modified hybrid tee, step recovery diodes, and bipolar transistors. For the first time a hybrid tee is used in ultra broad-band digital applications. Signal pulses with bit rates up into the gigabit-per-second range are regenerated, the shape of the input pulses having no direct influence on the shape of the output pulses. Only the charge of the input signals determines the amplitudes of the output pulses. At a signal bit rate of 1 Gbit/s an insertion voltage gain of 20 dB was obtained. Operating the DDR in a push-pull mode the voltage gain is doubled to 26 dB. Because the output pulses of the DDR are very narrow the circuit can be used in time-division multiplexers providing output pulse streams with bit rates up to 16 Gbit/s and amplitudes of several volts across a load of 50 Omega. The internal behavior of the DDR is analyzed, among other things by the results of computer simulations. Calculations for optimizing the employed components are given.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

High-bit-rate pulse regeneration and injection laser modulation using a diode circuit

The push-pull diode circuit investigated regenerates pulse trains near 1 Gbit/s with a power amplification of 8.4 dB. As a particular application, the direct modulation of a laser diode was carried out with this circuit at a bit rate of 1 Gbit/s.     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

基于行波电极电吸收调制􀀂 的高速光脉冲发生模块

速率高于40Gbit/s以上光脉冲发生器件是构建高速宽带光纤通信网络系统的关键，行波型电吸收调制器（TW－EAM）与分布反馈激光器（DFB－LD）的单片集成技术代表该领域的最新发展方向。本文利用准静态等效电路模型对行波型电吸收调制器的微波特性进行了分析并与实验室的实际测量结果进行了比较，得出了比较满意的结果。介绍了TW－EAMDFB－LD性能和最新的研究成果。     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

160 Gbit/s full optical time-division demultiplexing using FWM ofSOA-array integrated on PLC

160 Gbit/s full time-division demultiplexing using a semiconductor optical amplifier hybrid integrated demultiplexer on a planar lightwave circuit is demonstrated. Error-free, demultiplexing from a 160 Gbit/s signal to eight-channel, 20 Gbit/s signals is successfully demonstrated     

56 Gbit/s analogue PLL for clock recovery

A clock-recovery circuit is reported that employs a phase-locked loop (PLL) at 56.88 Gbit/s, and is demonstrated by locking to a 28.44 GHz sinusoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences. To the knowledge of the authors, this is the first demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s     

40 Gbit/s lumped-element modulator driver in GaAs pHEMTs

A high-speed and high-gain modulator driver circuit using 0.15 /spl mu/m gate length GaAs pHEMT technology is presented. The IC was developed for driving electroabsorption modulators in 40 Gbit/s optical fibre systems. To meet application requirements a lumped-element approach was used with differential configuration. Measured results show the circuit operates at 40 Gbit/s with a swing of 3 V/sub p-p/ for single-ended and 6 V/sub p-p/ for differential output, and 8/10 ps rise/fall times.     

超高速单电源GaAs判决再生电路

设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .5Gbit/s系列光通信系统