Magnetoresistive random access memory using magnetic tunnel junctions

Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.     

Flash [computer memory]

Ever falling chip geometries are beginning to raise serious doubts as to the long-term viability of flash. Quantum tunnelling is integral to the operation of flash memory, and as chips are getting smaller the ultra-thin tunnelling barrier is becoming increasingly prone to breaking down. A second problem is with the lifetime of flash-based devices, which can be limited to around 100000 cycles. This is fine for some applications, but inadequate where data storage requirements extend over decades. Flash is also quite slow and difficult to program, two problems that are getting more significant as chip areas increase and supply voltages fall. There are three technologies looking to replace flash: magnetic RAM (MRAM), ferroelectric RAM (FRAM) and ovonic RAM. All of these use new materials to create truly nonvolatile memories with long lifetimes. Getting any one of them to replace flash in the marketplace will depend on producing a sufficiently small memory cell, while at the same time minimising the number of additional processing steps required.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

MRAM空间粒子辐射效应关键技术研究

磁性随机存储器(MRAM)以其天然的抗辐射特性逐渐成为宇航电子系统的核心元器件之一.围绕MRAM空间粒子辐射效应关键技术,对MRAM辐射效应的研究背景、物理机制、研究方法等内容进行了论述.目前对MRAM的辐射效应研究主要集中在对商用MRAM芯片的辐射性能进行辐射实验评价,评价内容主要包括质子、中子、γ射线等空间粒子对芯...     

Board-level built-in self-repair method of RAM

This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units’ mapping and MCU can normally read and write external RAM. This design realizes the RAM’s built-in self-repairing on board.     

CMOS static RAM chip with high-speed optical read and write

We present the first demonstration of a dense VLSI RAM technology with high-speed optical read and optical write capability. The CMOS-based Static-RAM technology is capable of parallel optical access with read/write speeds limited by the native RAM access times. We fabricated a 2/spl times/2 mm optoelectronic-VLSI test chip incorporating 800-b storage and 200 optical I/O based on the hybrid integration of GaAs-AlGaAs MQW modulators on CMOS. Results from the photonic-SRAM test-chip confirm 6.2 ns read and 8-ns write capability.     

一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

An on-chip march pattern generator for testing embedded memorycores

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead     

Application and Improvement of Precise Resistance Tracing Technique for a Toggle Mode MRAM Evaluation

A precise evaluation technique was created for developing magnetoresistive random access memory (MRAM), especially memory that operates in a toggle-writing mode. This technique enables us to observe the detailed resistance transition of magnetic tunneling junction (MTJ) cells during complicated write operations. It was used to analyze incomplete operation and failed cells, and revealed that the MTJ characteristics in the third quadrant are significantly related to disturb robustness in megabit MRAM. To improve sensitivity to failed cells, we prepared 16-kbit MRAM test structures with a high-speed failed-cell check mode. We found our technique to be a powerful method of failure analysis and expect it to accelerate MRAM development.      

A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

铁电存储器在存储测试系统中的应用

为了实现环境试验的存储测试系统,采用了FRAM存储器M28W640结合SOC片上系统C8051F340的设计,通过分析其性能和接口电路,编写了相应的读写程序。由于这种并行非易失性存储测试技术方式具有高速读写、超低功耗、几乎无限次擦写,读写程序编写简便的优点,非常适合在此类存储测试系统中使用。     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

A circuit design of intelligent cache DRAM with automaticwrite-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current     

大容量Flash与DSP接口技术的实现

简要介绍了ATMEL公司的32Mbit并行Flash存储器AT49BV322T的特点,以及TI公司的DSP TMS320F2407A的主要性能特点。详细介绍了AT49BV322T的几种工作模式和操作方式,存储器与DSP的硬件接口技术,实现了DSP对多片超大容量并行存储器寻址的连续性。同时介绍了DSP对存储器在线编程的软件,包括对存储器的配置、读操作、写入操作以及片擦除操作等。     

基于March C-算法的单片机存储器测试

为了保证单片机系统的可靠性,对单片机内嵌存储器的测试显得尤为重要。根据MCS-51系列单片机系统内嵌存储器的结构特点和故障模型,研究了测试算法的选择、数据背景的产生等问题,首次提出将March C-算法用于单片机内嵌存储器的用户级测试程序编写。该测哉程序对SAF,TF,AF,CF的故障覆盖率可达到100％,并且能够检测部分NPSF故障,具有较高的故障覆盖率,适合于对用户级MCS-51系列单片机存储器的测试。     

Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.     

A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.     

Model for a 15 ns 16K RAM with Josephson junctions

An experimental memory model for investigating the feasibility of a 16K RAM memory with Josephson junctions was fabricated and tested. There are nearly 4500 Josephson junctions in the design which includes array, line drivers, and address decoders. Storage element is a single flux-quantum (SFQ) cell arranged in a 2K array. Drivers and decoders are based on the principle of current steering in superconducting loops, which is a medium speed but low power approach. The measured read-access time of the model is approximately 10 ns. Power dissipation of the unselected chip is zero, whereas for a read/write cycle time of 30 ns, it amounts to about 10 /spl mu/W. Results indicate that a 16K chip is feasible electrically. The estimated access time and power dissipation are 15 ns and 40 /spl nu/W, respectively.     

Spin-transfer torque RAM technology: Review and prospect

Non-volatile RAM (NV-RAM) enables instant-on/off computing, which drastically reduces power consumption. One of the most promising candidates for NV-RAM technology is the spin-transfer torque RAM (SPRAM) based on magnetic tunnel junction (MTJ) device technology. This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability. At the circuit level, a disruptive read operation for future large integration scale is described. A 4F² memory cell and a multi-bit cell approach are also presented. Finally, the potential value of instant-on/off computing through NV-RAM and its impact are explored.