A 32-Mb chain FeRAM with segment/stitch array architecture

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 /spl mu/m/sup 2/, which is smaller than a 0.13-/spl mu/m SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 /spl mu/A. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.     

Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure

A 0.18-/spl mu/m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi/sub 2/(Ta/sub x/Nb/sub 1-x/)/sub 2/O/sub 9/ (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10/sup 12/ at 85/spl deg/C and the data retention time up to 1000 h at 125/spl deg/C, which is the most promising for mass production of 0.18-/spl mu/m low-power system LSI-embedded FeRAM and beyond.     

A 0.25-/spl mu/m 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme

Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

FRAM design style utilising bit-plate parallel cell architecture

A new FRAM (ferroelectric RAM) design method, utilising a bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by the on-pitch plate control circuitry. It also reduces the power consumption in the memory array. Implementation results for a 0.13 /spl mu/m CMOS technology, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of a conventional structure.     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM scaling

Ferroelectric random access memories (FeRAMs) combine very attractive properties such as low-voltage operation, fast write and nonvolatility. However, unlike Flash memories, FeRAMs are difficult to scale along with the CMOS technology roadmap, mainly because of the decrease of available signal with decreasing cell area. One solution for further scaling is to integrate three-dimensional (3-D) FeCAPs. In this paper, we have integrated a 3-D FeCAP structure in a 0.35-/spl mu/m CMOS technology whereby the effective area of <1 /spl mu/m/sup 2/ single FeCAPs is increased by a factor of almost two. We show that, after optimization of the metal-organic chemical vapor deposition (MOCVD) deposition and post-anneal steps of the Sr/sub 0.8/Bi/sub 2.2/Ta/sub 2/O/sub 9/ (SBT) layer, the sidewall SBT contributes to the polarization Pr, resulting in higher Pr values for 0.81-/spl mu/m/sup 2/ three-dimensional (3-D) capacitors (2Pr/spl ap/15 /spl mu/C/cm/sup 2/) than for 1000 /spl mu/m/sup 2/ 2-D capacitors (2Pr/spl ap/10 /spl mu/C/cm/sup 2/). Moreover, these 3-D capacitors are observed to be fatigue-free and imprint-free up to 10/sup 11/ cycles (5-V square pulses), and extrapolations of retention tests indicate less than 10% Pr loss after ten years at 85/spl deg/C, which shows that sidewall SBT retains the same excellent reliability properties as 2-D capacitors. We demonstrate in this paper that the negative signal-scaling trend can be halted using 3-D FeCAPs. To our knowledge, this paper is the first report on electrical and reliability properties of integrated 3-D FeCAPs, and is a starting point for future development work on densely scaled FeRAMs.     

Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-/spl mu/m CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm/sup 2/ and the cell size is 0.121 /spl mu/m/sup 2/.     

A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm/sup 2/ 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-/spl mu/m CMOS process utilizing five layers of metal and two layers of poly.     

A 130-nm 0.9-V 66-MHz 8-Mb (256K /spl times/ 32) local SONOS embedded flash EEPROM

In a 0.13-/spl mu/m CMOS logic compatible process, a 256K /spl times/ 32 bit (8 Mb) local SONOS embedded flash EEPROM was implemented using the ATD-assisted current sense amplifier (AACSA) for 0.9 V (0.7 /spl sim/ 1.4 V) low V/sub CC/ application. Read operation is performed at a high frequency of 66 MHz and shows a low current of typically 5 mA at 66-MHz operating frequency. Program operation is performed for common source array with wide I/Os (/spl times/32) by using the data-dependent source bias control scheme (DDSBCS). This novel local SONOS embedded flash EEPROM core has the cell size of 0.276 /spl mu/m/sup 2/ (16.3 F/sup 2//bit) and the program and erase time of 20 /spl mu/s and 20 ms, respectively.     

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.     

A low-voltage, highly linear voltage-controlled transconductor

A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G/sub m/-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 /spl mu/m/sup 2/ and consumes an average power of 418 /spl mu/w at 125 Mbps and 1.8-V supply.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 /spl mu/m/sup 2/ is fabricated based on 0.13-/spl mu/m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V/sub t/ in erase while programming is done by lowering a local V/sub t/ through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.     

A new metal-ferroelectric (PbZr/sub 0.53/Ti/sub 0.47/O/sub 3/)-insulator (Dy/sub 2/O/sub 3/)-semiconductor (MFIS) FET for nonvolatile memory applications

Metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistors with Pb(Zr/sub 0.53/,Ti/sub 0.47/)O/sub 3/ ferroelectric layer and dysprosium oxide Dy/sub 2/O/sub 3/ insulator layer were fabricated. The out-diffusion of atoms between Dy/sub 2/O/sub 3/ and silicon was examined by secondary ion mass spectrometry profiles. The size of the memory windows was investigated. The memory windows measured from capacitance-voltage curves of MFIS capacitors and I/sub DS/-V/sub GS/ curves of MFIS transistors are consistent. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. A high driving current of 9 /spl mu/A//spl mu/m was obtained even for long-channel devices with a channel length of 20 /spl mu/m. The electron mobility is 181 cm/sup 2//V/spl middot/s. The retention properties of MFIS transistors were also measured.     

Fabrication and characterization of a new EEPROM cell with spacer select transistor

In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 /spl mu/m/sup 2/ with 0.18 /spl mu/m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests.     

NAND-type DRAM-on-SGT

In this brief, we propose a novel NAND-type DRAM-on-surrounding-gate transistor (SGT) architecture for high-density and low-voltage memory. The cell structure is composed of NAND-type DRAM vertically stacked on an SGT and an SGT-type capacitor. A cell size of 4F/sup 2/ can be achieved. Since it operates as a gain cell, it is possible to obtain a sufficient amount of signal charge. The device was fabricated with a 0.8-/spl mu/m lithography system.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.