A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

All-refractory GaAs FET using amorphous TiWSixsource/drain metallization and graded-InxGa1-xAslayers

We report on the fabrication of an all-refractory GaAs field-effect transistor having non-alloyed source and drain ohmic contacts and a TiW/Au refractory gate metallization. The ohmic contacts consist of amorphous TiWSi_x metallization and intervening graded InGaAs layers grown by low pressure organometallic vapor phase epitaxy (LPOMVPE). The amorphous TiWSi_x, is formed using alternating layers of TiW(10 Å) and Si(1.5 Å) deposited by an RF magnetron sputtering technique. The resulting all-refractory FET devices exhibited excellent dc transistor characteristics with measured transconductance of 140 mS/mm. The dc performance of these devices was comparable to conventional devices with AuGe/Ni/Au contacts fabricated using similar material structures     

GaAs field effect transistors fabricated by imprint lithography

A GaAs metal–semiconductor field-effect transistor (MESFET) has been realized based on mix-and-match fabrication using optical lithography for the ohmic contacts and imprint lithography for the gate. The gate length and width are 1.2 and 80 μm, respectively, the channel length is 4 μm. For the gate definition a Si-mold is embossed into a thin polymer film located on top of an n-doped GaAs layer. The gate is fabricated by metal evaporation and lift-off.     

A new self-aligned GaAs FET with a Mo/WSixT-gate

An n+-layer and ohmic electrode self-aligned (NOSA) GaAs FET is a new self-aligned GaAs FET in which n⁺-layers and ohmic contacts in the source and the drain regions are self-aligned to a T-shaped gate formed with Mo and WSix(≈0.6) double layers. Using the NOSA FET structure, the device area can be easily reduced because no alignment margin is needed. The fabricated FET's exhibit a transconductance gmof 170 mS/mm.     

Amorphous-Silicon gate GaAs FET's

Silicon-germanium-boron ternary amorphous alloy has been applied to GaAs FET as a gate contact material. A good Schottky contact with a barrier height as large as 0.94 V has been realized. Schottky-barrier gate GaAs FET's fabricated using the amorphous film as a gate contact layer exhibit excellent normally off FET characteristics of a large saturated drain curent, which has never been attained by conventional GaAs MESFET's.     

High-temperature stability of refractory-metal VLSI GaAs MESFETs

Commercially available, self-aligned VLSI GaAs MESFETs, with tungsten-based refractory-metal Schottky gates, nickel-based refractory-metal ohmic contacts, and aluminum interconnection metallization, have been thermally cycled and shown to be stable after 3 h at temperatures up to 500°C. Both partially processed and fully processed wafers were found to be stable with no significant change occurring in either Schottky gate or ohmic contact properties. An increase in the channel resistance component of the series resistance is believed to be responsible for I_DS and g_m degradation above 500°C. The fact that commercially available, gold-free VLSI GaAs MESFETs are able to withstand such thermal cycles has very important consequences for monolithic optoelectronic integrated circuit (OEIC) fabrication because it means that it may now be feasible to grow photonic device heterostructures epitaxially on MESFET VLSI wafers; process them into lasers, modulators, and/or detectors; and interconnect them with the electronics to produce VLSI-density OEICs     

High-quality schottky and ohmic contacts in planar 4H-SiC metal semiconductor field-effect transistors and device performance

We have fabricated planar 4H-SiC, metal-semiconductor field-effect transistors (MESFETs) with high-quality metal/SiC contacts. To eliminate potential damage to the gate region caused by etching and simplify the device fabrication process, gate Schottky contacts were formed without any recess gate etching, and an ideality factor of 1.03 was obtained for these gate contacts. The interface state density between the contact metal and SiC was 5.7×10¹² cm⁻²eV⁻¹, which was found from the relationship between the barrier height and the metal work function. These results indicate that the interface was well controlled. Thus, a transconductance of 30 mS/mm was achieved with a 3-μm gate length as the performance figure of these MESFETs with high-quality metal/SiC contacts. Also, a low ohmic contact resistance of 1.2×10⁻⁶ Θcm² was obtained for the source and drain ohmic contacts by using ion implantation.     

A molybdenium source,gate and drain metallization system for GaAs MESFET layers grown by molecular beam epitaxy

Molecular beam epitaxy has been used in a continuous growth procedure to form GeGaAs epitaxial structures that were suitable for MESFET fabrication. Near surface doping profiles were engineered such that low resistance ohmic contacts to the GaAs layer were obtained by subsequently depositing a metal overlayer on the Ge surface. Evaporated Au overlayers yielded specific contact resistances of the order of 10^?6ω cm² without heat treatment. Because the conventional alloying procedure now appeared superfluous, metallurgically non-reactive systems were investigated with a view to constructing GaAs MESFETs with entirely refractory metallizations. Sputtered molybdenum has been evaluated for both the formation of ohmic contacts to the Ge/GaAs layers and rectifying contacts to the GaAs layer. Damage introduced as a result of the sputtering deposition process is the probable cause of non-ideality in the as-prepared Schottky barriers. However, forward bias current-voltage ideality factors of n = 1.07 have been obtained after annealing.     

The fabrication of Ga1-xAlxAs-GaAsheterojunction bipolar transistors for rapid material analysis

We report a procedure for fabricating Ga_1-xAl_x As-GaAs heterojunction bipolar transistors with a single Al-Ge-Ni metallization step for rapid material analysis. Al-Ge-Ni produces an excellent ohmic contact to both n- and p-type GaAs, and eliminates the need for two metallization steps to produce the three transistor contacts. Complete transistor fabrication, which includes separate etching steps to the base and the subcollector, can be carried out in approximately four hours. We have used this rapid turnaround time to enhance wafer yield by minimizing the lag time between the onset of a growth problem or reactor hardware problem and subsequent growth runs     

Fabrication and characterization of a depletion-mode ZnS0.07Se0.93 MESFET

We report the fabrication and characterization of a depletion-mode n-channel ZnS_0.07Se_0.93 metal-semiconductor field effect transistor (MESFET). A ZnSSe FET could be a key element in opto-electronic integration consisting of light emitters, light receivers and MESFET pre-amplifiers. Mesa isolation, recess etching and self-alignment techniques were adopted to optimize the MESFET performance. Source and drain (S/D) ohmic contacts and gate Schottky contact were formed by Cr/In/Cr and Au deposition, respectively. Depletion mode FET's with varying gate width-to-length ratio of W/L=200 μm/20 μm, 200 μm/4 μm and 200 μm/2 μm were fabricated. A 2 μm FET was characterized as follows: the turn-on voltage, V_on≈1.75 V, the pinch-off voltage, V_p≈-13 V, the unit transconductance, g_m≈8.73 mS/mm, and the breakdown voltage with zero gate-source bias, BV≈28 V     

Si衬底上MBE GaAs MESFET与IC制备

叙述在MBE(分子束外延)GaAs/Si材料上制作GaAs MESFET与Ic的研究。考虑到GaAsIC与Si IC单片集成的需要,采用了Ti/TiW/Au肖特基金属化和Ni/AuGe/Ni/Au欧姆接触金属化,层间介质采用等离子增强淀积氮化硅和聚酰亚胺复合材料。在该工艺基础上,制备了性能良好的GaAs/Si MESFET与IC。     

Use of Sn-doped GaAs for non-alloyed ohmic contacts to HEMTs

Segregation of Sn to the surface of MBE grown n⁺-GaAs layers allows fabrication of non-alloyed Ti/Pt/Au, Al or Ti/W ohmic contacts with low specific contact resistivities (1.1×10^-6 Ω·cm^-2). These contacts were used to realise high performance HEMTs (g_m=230 mS/mm for 1.0 μm gate length) in which Si is used as the dopant in the donor AlGaAs layer and Sn is employed in the GaAs contact layer     

A self-aligned ohmic metallization GaAs-Gate FET with integrated coupling diode

A novel processing scheme has been demonstrated for the fabrication of GaAs/AlGaAs semiconductor-insulator-semiconductor FET's (SISFET's). It was shown that a self-aligned ohmic (SAO) metal deposition could be used, without any additional ion implantation, to contact the two-dimensional electron gas (2DEG) of the SISFET. The process incorporates a coupling diode epitaxially grown atop the semiconductor gate (CDFL scheme [1]). Also, a depletion-mode MESFET was fabricated within the GaAs-gate layer in order to demonstrate the feasibility of a SISFET/MESFET inverter.     

Ohmic contact formation in palladium-based metallizations to n-Type InP

Two Pd-based metallizations have been systematically studied, i.e., Au/Ge/Pd and Pd/Ge contacts to n-type InP, in an attempt to better understand the role of the metallization constituents in forming ohmic contacts. Ohmic contacts were obtained with minimum specific resistances of 2.5 × 10⁻⁶ Ω-cm² and 4.2 × 10⁻⁶ Ω-cm² for the Au/Ge/Pd and the Pd/Ge contacts, respectively. The annealing regime for ohmic contact formation is 300-375°C for the Au/Ge/Pd/InP system and 350-450°C for the Pd/GelnP system. Palladium, in both cases, reacts with InP to form an amorphous layer and then an epitaxial layer at low temperatures, providing good metallization adhesion to InP substrates and improved contact morphology. Ohmic contact formation in both contacts is attributed to Ge doping, based on the solid state reaction-driven decomposition of an epitaxial layer at the metallization/InP interface, producing a very thin, heavily doped InP layer. Gold appears to be responsible for the difference in contact resistance in the two systems. It is postulated that Au reacts strongly with In to form Au-In compounds, creating additional In site vacancies in the InP surface region (relative to the Au-free metallization), thereby enhancing Ge doping of the InP surface and lowering the contact resistance. Both contacts degrade and ultimately become Schottky barriers again if over annealed, due to consumption of additional InP, which destroys the heavily doped InP layer.     

Reliability of the structure Au/Cr/Au-Ge/Ni/GaAs in lownoise dual gate GaAs FET

The first report based only on measurements using AES (Auger Electron Spectroscopy) profiles in GaAs FET with Al gate (ohmic contact Au-Ge/Ni/GaAs; Schottky contact Au/Cr/Al/GaAs) is presented.Six mm wide dual gate GaAs devices have been aged with and without DC bias conditions at different temperatures ranging from room temperature to 275°C. Other kinds of stresses have been made on these kind of devices like surge pulse test and endurance in humid ambiance.The different mechanisms which are involved in the degradation of the electrical characteristics are investigated and some correlation are established with the effects observed on the profiles of the elements constituting the ohmic contact and the gate contact.For each mechanism, the activation energy is given as well as the MTTF. By this way a prediction of what mechanism can cause the failure is obtained.Other use of the AES profiles can be made to find out all the parameters of the ohmic contact formation (layer thickness, annealing temperature).A new interpretation of the contact resistance increase is given by the support of AES profiles and fitting of experimental degradation with activation energy determination.     

反应溅射法制备耐熔金属氮化物/GaAs肖特基结

自对准GaAs场效应晶体管工艺要求非常稳定的材料作为栅电极,经高温退火过程后它仍必须与衬底保持良好的肖特基接触。本文总结了近几年来有关耐熔金属氮化物/GaAs肖特基结的研究工作,对取得的进展及存在的问题进行了讨论。     

Use of Au/Te/Ni films for ohmic contact to GaAs

Ohmic contacts to n-type GaAs are usually fabricated by alloying AuGe/Ni films on GaAs. Ge acts as a donor to GaAs for fabrication of the ohmic contact. In an attempt to replace Ge, which is an amphoteric impurity, with a group VI element to improve on the ohmic contact resistivity, experiments were done with AuTe and AuTe/Ni contacts. A very low resistivity of ∼5 × 10^-7Ω.cm²was obtained by alloying 1700 Å of AuTe film with 300 Å of nickel on top at 510°C. This is the lowest contact resistivity obtained with any material other than AuGe/Ni on n-type GaAs.     

Heterostructure devices using self-aligned p-type diffused ohmiccontacts

Describes the use of a p-type refractory ohmic contact in ohmic self-aligned devices. The contacts are based on self-aligned diffusion of zinc-doped tungsten film. The diffusion is nearly isotropic in the vicinity of silicon nitride sidewalls, allowing self-alignment of ohmic contacts with emitters and gates. Low-resistance contacts (<10^-6 Ω·cm²) are formed both to GaAs and GaAlAs, and the lifetime of the diffused region is superior to that obtained from implantation. Heterostructure bipolar transistors (HBTs) showing high current gains (⩾50 at 2×10³ A·cm^-2 and ⩾200 at 1×10⁵ A·cm^-2 with micrometer-sized emitter widths) and p-channel GaAs gate heterostructure field-effect transistors (HFETs) showing high transconductances (78 mS/mm at 2.2-μm gate length) have been fabricated using this contact     

Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

Novel fully self-aligned MESFET using source and drain regrown nonalloyed contacts by ALE

A new low temperature, nonalloyed, self-aligned FET process using regrowth technology on a patterned substrate has been demonstrated. A double 8-doped MESFET with regrown n⁺⁺ source and drain contact regions using atomic layer epitaxy (ALE) were fabricated and characterized. In this novel regrowth technique, a silicide gate was embedded by molybdenum and a side wall oxide to prevent any contamination or unwanted reaction during the ALE growth. Two main features associated with our process that makes it an attractive technology for more uniform device performance across a large area wafer are: a) the refractory gate/GaAs interface is not subjected to any high temperature process, and b) nonalloyed ohmic contacts are achieved without undesirable lateral diffusion of n⁺ regions caused by annealing of implanted source and drain. The preliminary unoptimized device results show a transconductance of 40 mS/mm for gate length of 0.65 μn.