共查询到18条相似文献,搜索用时 109 毫秒
1.
2.
徐晓飞 《微电子学与计算机》2006,23(2):148-150
日前广泛使用的交换机采用输出队列结构,系统可扩展性差、通信速度有限等缺点。文章提出一种基于输入队列的新型交换机结构,通过采用双口存储器来实现交换机的输入缓冲区,通过多数据包查询技术来提高交换机的通信性能。分析结果表明:文章设计的交换机系统吞吐量可达到理论吞吐量的95.748%.接近于输出队列交换机,但需要的存储器带宽只有输出队列交换机的1/N为交换机的端口数),大大提高了系统的可扩展性。 相似文献
3.
输入队列(IQ)交换机在采用虚输出队列(VOQ)技术基础上,能够提供低成本的高速交换机,但在一般调度算法下,IQ交换机缺乏保证QoS的能力。本文在Birkhoff和Von Neumann研究的基础上运用随机过程理论和网络计算理论提出一种预留带宽的调度算法,并分析了相关的延迟上界和VOQ需要的内存情况。 相似文献
4.
5.
针对混合输入-交叉点队列(CICQ)交换结构受限于"流控通信延时"、"需要2倍内部加速仿真输出队列(OQ)交换"以及单纯交叉点缓冲(CQ)存在"非均衡流量模式下吞吐量性能不足"等问题,本文提出一种新型的"负载均衡交叉点缓冲交换结构".采用固定模式时隙轮转匹配进行负载均衡处理,将到达输入端口的非均衡流量转化为近似均衡流量并且平均分配到同一输出端口对应的交叉缓冲中,从而可以利用较小的交叉点缓冲来模拟输出队列调度,简化调度过程并且提高吞吐量.理论分析证明了这种新结构的稳定性以及模拟输出队列交换的能力.同时仿真表明,采用该交换结构可以在不需要内部加速的条件下获得相当于输出队列交换的性能,并且有效地解决了交叉点缓冲队列非均衡流量性能不足的问题. 相似文献
6.
一种基于最长队列预测的CICQ交换结构调度算法 总被引:1,自引:1,他引:0
CICQ(Combined Input Crosspoint Queued)是一种在crossbar交叉点加入少量缓存的交换结构,具有无需内部加速比及分布并行调度的特性。为了自适应网络环境中各种业务流量,提高在非均匀流量下的性能,该文提出了一种基于最长队列预测的高效CICQ交换结构调度算法RR-LQD (Round Robin with Longest Queue Detecting)。RR-LQD算法复杂度为O(1),具有良好的可扩展性;通过预测局部最长队列并尽力为其服务,保持调度中队列长度的均衡,能够适应各种非均匀流量的网络环境。仿真结果表明:在各种均匀和非均匀流量下,RR-LQD算法均能达到100%的吞吐量,并且具有优良的时延性能。该文使用FPGA芯片实现了RR-LQD算法仲裁器,能够满足高速、大容量交换结构的设计需要。 相似文献
7.
8.
9.
带虚拟输出队列(VOQ)的输入队列(IQ)交换结构可按比例地达到很高的速度,甚大规模集成电路(VLSI)集成度的不断提高使得对于Crossbar的交叉点在硬件上为每个信元或包留有足够的缓存成为可能。采用组合输入/输出排FX(CICQ)交换,可利用简单的算法得到比IQ交换更低的延迟。 相似文献
10.
11.
H. Jonathan Chao Cheuk H. Lam Xiaolei Guo 《International Journal of Communication Systems》2001,14(7):663-678
Input–output queued switches have been widely considered as the most feasible solution for large capacity packet switches and IP routers. In this paper, we propose a ping‐pong arbitration scheme (PPA) for output contention resolution in input–output queued switches. The challenge is to develop a high speed and cost‐effective arbitration scheme in order to maximize the switch throughput and delay performance for supporting multimedia services with various quality‐of‐service (QoS) requirements. The basic idea is to divide the inputs into groups and apply arbitration recursively. Our recursive arbiter is hierarchically structured, consisting of multiple small‐size arbiters at each layer. The arbitration time of an n‐input switch is proportional to log4?n/2? when we group every two inputs or every two input groups at each layer. We present a 256×256 terabit crossbar multicast packet switch using the PPA. The design shows that our scheme can reduce the arbitration time of the 256×256 switch to 11 gates delay, demonstrating the arbitration is no longer the bottleneck limiting the switch capacity. The priority handling in arbitration is also addressed. Copyright © 2001 John Wiley & Sons, Ltd. 相似文献
12.
1 IntroductionActivenetworks[1 ] are packet switchednet worksinwhichpacketscancontaincodefragmentsthatareexecutedontheintermediarynodes.Thecodecarriedbyapacketmayextendandmodifythenetworkinfrastructure .Thegoaloftheactivenet workresearchistodevelopmechanis… 相似文献
13.
An evolution to crossbar switches with virtual output queuing and buffered cross points 总被引:2,自引:0,他引:2
Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem. 相似文献
14.
Queueing in high-performance packet switching 总被引:14,自引:0,他引:14
The authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch. They are (1) input queuing, where a separate buffer is provided at each input to the switch; (2) input smoothing, where a frame of b packets is stored at each of the input line to the switch and simultaneously launched into a switch fabric of size Nb ×Nb ; (3) output queuing, where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and (4) completely shared buffering, where all queuing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N , but is approximately 0.586 with FIFO buffers when N is large. Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queuing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size 相似文献
15.
本文采用带缓存交叉开关作为核心交换单元,构建了一种空分复用扩展的联合输入/交叉节点/输出排队(SDM-CICOQ)交换结构,从理论上证明了当扩展因子为2时,SDM-CICOQ交换结构可以获得100%的吞吐量,并且能够完全模拟输出排队(OQ)交换结构,从而能够提供服务质量(QoS)保障.本文还给出了一种层次化优先级调度(HPS)方案作为SDM-CICOQ交换结构调度机制的工程设计参考,仿真结果表明采用HPS调度方案SDM-CICOQ交换结构可获得良好的性能. 相似文献
16.
Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log2 N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log2 N time periods. Performance analysis shows that the additional delay is small. 相似文献
17.
An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation 相似文献
18.
该文提出了一种新的并行分组交换(PPS)网络调度算法。该算法通过在解复用器处采用以变长分组为业务分配单元的方式消除了信元的乱序问题;通过采用Credit机制进行业务分配,实现了业务到各个交换平面完全公平的分配;各个并行交换单元采用组合输入输出排队,降低了对缓存和交换平面的加速要求,同时可以充分利用现有单Crossbar网络调度算法的研究成果。文中证明了该算法对业务分配的公平性,对高速缓存的需求量以及整个网络的稳定性,仿真进一步证明了该算法具有良好性能。 相似文献