A fault-tolerant 30 ns/375 mW 16K/spl times/1 NMOS static RAM

A fault-tolerant 30950 mil/SUP 2/ (19.9 mm/SUP 2/) 16K/spl times/1 static MOS RAM has been fabricated with a single polysilicon E/D NMOS process. Using circuit techniques normally restricted to dynamic RAMs, but adapted for asynchronous operation, the device achieves a typical access time of 30 ns while dissipating only 375 mW. Among the topics discussed in a new single-polysilicon memory cell configuration, the first truly asynchronous bootstrap circuit, an active bit-line equilibration and precharge scheme, and a new power-efficient substrate bias generator. Also described is an on-chip redundancy scheme which consumes approximately 2 percent of the total chip area, does not compromise access time and can be programmed using standard test equipment.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

SNOS 1K/spl times/8 static nonvolatile RAM

Using an advanced n-channel, double level polysilicon SNOS technology, a 1K/spl times/8 bit nonvolatile static RAM has been designed. Typical RAM access time is 300 ns, with typical active power dissipation of 300 mW, and standby power of 160 mW. Endurance of 10/SUP 4/ erase/store cycles has been demonstrated. The ability to measure erased and written memory thresholds allows prediction of retention lifetime. For the 8K NVRAM, the minimum retention lifetime is 1 year following a 10 ms erase and store.     

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.     

A 4.5 ns access time 1K /spl times/ 4 bit ECL RAM

An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.     

A 100 ns 5 V only 64K/spl times/1 MOS dynamic RAM

A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL negative undershoot protection on address circuits, and 7) active hold-down transistors for both X and Y drivers. A nominal 100 ns access time and power dissipation of less than 150 mW was observed during active operation with a 20 mW power dissipation in the standby mode.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

A Hi-CMOSII 8K/spl times/8 bit static RAM

A Hi-CMOSII static RAM with 8K word by 8 bit organization has been developed. The RAM is fabricated using double polysilicon technology and p- and n-channel transistors having a typical gate polysilicon length of 2 /spl mu/m. The device was realized using low-power high-speed-oriented circuit design and a new redundancy circuit that utilizes laser diffusion programmable devices. The new RAM has an address access time of 65 ns, operating power dissipation of 200 mW, and standby dissipation of 10 /spl mu/W.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

A 16 ns 2K/spl times/8 bit full CMOS SRAM

A high-speed 2K/spl times/8 bit full CMOS SRAM fabricated with a platinum silicide gate electrode and single-level aluminum technology is described. A typical address access time of 16 ns, which is comparable to the 16-kb bipolar SRAMs, was achieved. Typical active and standby power dissipations are 150 mW and 25 nW, respectively. The platinum silicide word line reduces the total address access time by 25%. A compact cell layout design, as well as a 1.5-/spl mu/m device feature size, also gives fast access time. The properly controlled bit line swing voltage provides reliable and fast readout operation. The chip size of the SRAM is 2.7/spl times/3.5 mm.     

A fast 32 K/spl times/8 CMOS static RAM with address transition detection

A high-speed 256 K (32 K/spl times/8) CMOS static RAM (SRAM) is described. Precharging and equalization schemes are implemented with address-transition-detection (ATD) techniques. With a differential sensing circuitry, a 23-ns access time is achieved (at V/SUB cc/=5 V and 25/spl deg/C) for addresses and chip-select clocks. The operating current is 36 mA in the READ cycle and 28 mA in the WRITE cycle, at 10-MHz cycling frequency. A four-transistor memory cell is designed with double-polysilicon and double -metal layers to achieve high performances. Versatile redundancy schemes consisting of polysilicon laser fuses, logical circuitry, and novel enable/disable controls are designed to repair defective cells. A compensation circuit is used to optimize writing parameters for redundant columns.     

A high-speed ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time

An ECL 100K compatible 64/spl times/4 bit RAM with 6 ns access time, 600 mW power dissipation, and a chip size of 4.8 mm/SUP 2/ has been developed for caches and scratchpad memories to enhance the performance of high-speed computer systems. The excellent speed performance together with the high-packing density has been achieved by using an oxide isolation technology in conjunction with novel circuit techniques. The device is adaptable to modern subnanosecond logic arrays, and, hence, is a member of the Siemens SH 100 family.     

Circuit techniques for a 25 ns 16K/spl times/1 SRAM using address-transition detection

The authors describe special circuit techniques that have been used to produce a 25-ns HMOS 16K/spl times/1 SRAM. In particular, a new dynamic row-decoder driver, hold-valid-data output driver, and column-decoder driver have been developed. A new memory clear function, called the bulk-write feature, that writes all data locations to the same data as the data-in pin in one long (/spl sime/700 ns) write cycle was also developed. This 16K/spl times/1 SRAM has a die area of 25.3K mil/SUP 2/ (16.3 mm/SUP 2/), and was fabricated using a 2-/spl mu/m double-polysilicon NMOS technology.     

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

A 4K/spl times/8 dynamic RAM with self-refresh

A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, counter and multiplexer. A high-speed arbiter resolves simultaneous memory and refresh requests. Redundant rows are used for increased manufacturing yields. Polysilicon fuses are electrically programmed to select redundant rows.     

A 128K word/spl times/8 bit dynamic RAM

A 1-Mb DRAM with 128K/spl times/8 bit organization is described. In designing the circuit, half V/SUB cc/ bit line precharge with dummy reverse circuits was adopted for noise reduction. The noise is estimated using a three-dimensional capacitance calculation. In realizing the chip, a 1-/spl mu/m NMOS process with double-level aluminum wiring was used.     

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA.