Yield prediction via spatial modeling of clustered defect counts across a wafer map

In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP) regression. Analysis results indicate that yield prediction can be greatly improved by capturing the spatial distribution of defects across the wafer map. In particular, the ZIP model with spatial covariates shows considerable promise as a yield model since it additionally models zero-defective chips. The modeling procedures are tested using a practical example.     

Wafer yield prediction using derived spatial variables

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use in the literature. This paper proposes a novel wafer yield prediction model that incorporates the spatial clustering information in functional testing. Fused LASSO is first adopted to derive variables based on the spatial distribution of defect clusters. Then, a logistic regression model is used to predict the final yield (ratio of chips that remain functional until expected lifetime) with derived spatial covariates and functional testing values. The proposed model is evaluated both on real production wafers and in an extensive simulation study. The results show that by explicitly considering the characteristics of defect clusters, our proposed model provides improved performance compared to existing methods. Moreover, the cross‐validation experiments prove that our approach is capable of using historical data to predict yield on newly produced wafers.     

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Theory of single-current domain propagation circuits

Single-current propagation circuits cause circular magnetic domains in a uniaxial ferrimagnetic wafer to move continuously by properly combining dynamic and static forces which vary periodically with distance. The dynamic force is due to a current and varies periodically with time at a frequencyf. The static force has a spatial period one-half the period of the dynamic force. The static force may be produced by a periodic array of Permalloy elements or by a periodic modulation of wafer thickness. The general principle is discussed and a simple mathematical model is used to indicate the optimum amplitude and phase of the static force relative to the dynamic force. Single-current propagation circuits [1] cause circular magnetic domains in a uniaxial ferrimagnetic wafer to move continuously by properly combining dynamic and static forces which vary periodically with distance and have an average value of zero. The dynamic force is due to a current and varies periodically with time at a frequencyf. The second is static and has a spatial period one-half the period of the dynamic force. The static force may be produced by a periodic array of Permalloy elements [2], [3] or by a periodic modulation of wafer thickness [4]. The general principle is outlined in Figs. 1 and 2.     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

A triple axis mode X-ray diffraction measurement on elastic strain distribution of lightly Cr-doped SI-GaAs for laser windows

The triple axis mode X-ray diffraction method is described, which has been used to measure the spatial variation in the lattice parameters of {1 0 0} lightly Cr-doped SI-GaAs laser windows. It has been found that a remarkable spatial variation of elastic strain exists in the window wafer. The results show that the thinner the wafer is, the smaller the stress spatial variation in the wafer. The elastic strain in the window wafer can be released by thermal annealing. The method can also be applicable to the precise lattice parameter measurements of the compound materials.     

硅晶圆磨削减薄工艺的磨削力模型

硅晶圆磨削减薄是一种有别于传统磨削的材料加工方式。磨削减薄过程中,硅晶圆和砂轮同时绕旋转轴旋转,砂轮沿垂直方向连续进给去除材料,其中磨削力是磨削质量的决定性因素。目前,尚缺少一个用于硅晶圆磨削减薄工艺的磨削力预测模型。为了得到磨削力模型,分析了磨削减薄过程中的硅晶圆材料去除机理,将磨削力分为摩擦力和切屑力,考虑了磨粒运动轨迹,分别计算了单颗磨粒在法向和切向上的摩擦力和切屑力,最后基于有效磨粒总数建立了总磨削力模型。模型综合考虑了磨削参数、砂轮和硅晶圆的几何参数和材料性质对磨削力的影响。讨论了砂轮进给速度、晶圆转速和砂轮转速三个主要磨削参数对磨削力的影响,讨论了硅晶圆上晶向对磨削力的影响,给出了磨削力在硅晶圆面上沿径向的分布情况。     

Analysis of integrated circuit fault data using generalized linear models

Fault data for integrated circuits manufactured on silicon wafers are usually presented using wafer maps to indicate the spatial distribution of defects. This paper shows how this type of spatial data can be analyzed under the framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fault sources with assignable causes that may possibly be eliminated with process improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the faults are distributed non‐uniformly across the wafer. Furthermore, we demonstrate how designed experiments can be used in optimizing the setting of important process parameters. Copyright © 2000 John Wiley & Sons, Ltd.     

Local Stress Field in Wafer Thinning Simulations with Phase Space Averaging

From an ingot to a wafer then to a die, wafer thinning plays an important role in the semiconductor industry. To reveal the material removal mechanism of semiconductor at nanoscale, molecular dynamics has been widely used to investigate the grinding process. However, most simulation analyses were conducted with a single phase space trajectory, which is stochastic and subjective. In this paper, the stress field in wafer thinning simulations of 4H-SiC was obtained from 50 trajectories with spatial averaging and phase space averaging. The spatial averaging was conducted on a uniform spatial grid for each trajectory. A variable named mask was assigned to the spatial point to reconstruct the shape of the substrate. Different spatial averaging parameters were applied and compared. The result shows that the summation of Voronoi volumes of the atoms in the averaging domain is more appropriate for spatial averaging. The phase space averaging was conducted with multiple trajectories after spatial averaging. The stress field converges with increasing the number of trajectories. The maximum and average relative difference (absolute value) of Mises stress was used as the convergence criterion. The obtained hydrostatic stress in the compression zone is close to the phase transition pressure of 4H-SiC from first principle calculations.     

Modeling and calculation of slurry-chemistry effects on chemical–mechanical planarization with a grooved pad

During chemical–mechanical planarization (CMP), a rotating wafer is pressed against a rotating pad, while a slurry is dragged into the pad–wafer interface. Here, taking into account the dependence of local material removal rate (MRR) on the slurry’s chemical activity, the effects of pad groove geometry and various other process parameters on the spatial average and non-uniformity of MRR are examined. Technically, the slurry flow is calculated by following an existing approach that integrates two-dimensional fluid-film lubrication theory and contact-mechanics models. A slurry impurity transport equation is then used to calculate the impurity concentration that determines the slurry’s chemical activity and hence the local MRR. The numerical results obtained here indicate that the presence of pad grooves generally decreases the average slurry impurity concentration, and increases the average contact stress on the pad–wafer interface. However, as a grooved pad has less contact area for effective interaction with the wafer surface, the average MRR may or may not be increased, depending upon the specific setting of process parameters. Meanwhile, it appears that the retaining ring generally used to keep the wafer in place also plays an important part in reducing the MRR non-uniformity.     

Performance of GaN vertical light emitting diodes using wafer bonding process with Al-alloyed graphite substrate

We report on the vertical-structure light emitting diodes (VLEDs) fabricated with wafer bonding method using Al-alloyed graphite and Si supporter. VLEDs with Al-alloyed graphite produced no crack during/after laser lift-off (LLO) techniques while the wafer crack took place using Si supporter because of the difference of thermal expansion coefficients between Si and sapphire. The performance of VLEDs with wafer bonding method using Al-alloyed graphite supporter was compared to those fabricated by Cu plating methods. The output power of the chips with wafer bonding method was nearly same as the one with Cu-plating method. However, the forward voltage of VLEDs with wafer bonding method was higher than those with Cu-plating method. In the terms of reliabilities the wafer bonding process is more preferable to Cu-plating and our report proposes that Al-alloyed graphite could be one of promising candidates for the supporters in wafer bonding process.     

The Future of Microelectromechanical systems (MEMS)

Abstract:  MEMS-based products produced in 2005 had a value of $8bn, 40% of which was sensors. The balance was for products that included micromachined features, such as ink jet print heads, catheters and RF IC chips with embedded inductors. Growth projections follow a hockey stick curve, with the value of products rising to $40bn in 2015 and $200bn in 2025! Growth to date has come from a combination of technology displacement, as exemplified by automotive pressure sensors and airbag accelerometers and new products, such as miniaturised guidance systems for military applications and wireless tire pressure sensors. Much of the growth in MEMS business is expected to come from products that are in the early stages of development or yet to be invented. Some of these devices include disposable chips for performing assays on blood and tissue samples, which are now performed in hospital laboratories, integrated optical switching and processing chips, and various RF communication and remote sensing products.The key to enabling the projected 25-fold growth in MEMS products is development of appropriate technologies for integrating multiple devices with electronics on a single chip. At present, there are two approaches to integrating MEMS devices with electronics. Either the MEMS device is fabricated in polysilicon, as part of the CMOS wafer fabrication sequence or a discrete MEMS device is packaged with a separate ASIC chip. Neither of these approaches is entirely satisfactory, though, for building the high-value, system-on-chip products that are envisioned. It is this author's opinion that a combination of self-assembly techniques in conjunction with wafer stacking, offer a viable path to realizing ubiquitous, complex MEMS systems.     

The infrastructure of the timed EOPNs-based multiple-objective real-time scheduling system for 300 mm wafer fab

Modern semiconductor wafer fabrication systems are changing from 200?mm to 300?mm wafer processing, and with the dual promises of more chips per wafer and economy of scale, leading semiconductor manufacturers are attracted to developing and implementing 300?mm wafer fabs. However, in today's dynamic and competitive global market, a successful semiconductor manufacturer has to excel in multiple performance indices, such as manufacturing cycle time and on-time delivery, and simultaneously optimize these objectives to reach the best-compromised system achievement. To cope with this challenge, in this paper, the infrastructure of a timed EOPNs-based multiple-objective real-time scheduling system (MRSS) is proposed to tackle complex 300?mm wafer fabs. Four specific performance objectives pursued by contemporary semiconductor manufacturers are integrated into a priority-ranking algorithm, which can serve as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the real-time state-dependent dispatching system. This dispatching control system is timed EOPN-based and adopts a heterarchical organization that leads to a better real-time performance and adaptability. As the foundation of real-time schedule, the timed EOPNs modelling approach is expounded in detail, and the prototype of the MRSS simulation system is also provided.     

Scheduling and optimization of mixed-processing with multi-variety wafers in dual-armed cluster tools

ABSTRACT

To improve the efficiency of wafer fabrication, this work addresses the scheduling and control problems of mixed-processing with multiple wafer types in cluster tools. Then, based on a developed Petri net (PN) model, it presents a general model for cluster tools with multiple wafer types and the conventional swap strategy. By analyzing the coordination mechanism between wafers processing and robot tasks, necessary and sufficient conditions are established to check the schedulability of the system that is operated by using the conventional swap strategy. If the system is not schedulable checked by such schedulability conditions, a constraint-guided heuristic algorithm and a conflicts-avoiding algorithm are developed to obtain a reasonable schedule. Finally, illustrative examples are presented to show the applications of the proposed method.     

Study of chip strength due to backside grinding on wafer

Abstract

The strength distribution of semiconductor chips on a wafer was studied for this paper using the three‐point bending test method that complies with ASTM standard E855. It was found from thousands of testing results that a weak region in a wafer always exists when the wafer has been thinned by mechanical backside grinding method. This weak region was distributed in two sectorial regions 45 degrees wide and symmetric to the wafer center. The averaged chip strength in the weak region was found to be at least 30% lower than the averaged chip strength of the whole wafer, and was independent of chip aspect ratio, metallization, diameter of the wafer, and the equipment that the backside grinding process used. The existence of the weak region was due to the grinding mark produced by the equipment, and was physically explained by the experimental results in this study. This weak region was able to be eliminated by using either plasma etching or polishing after the mechanical backside grinding.     

Micro data-loggers lead to two new classes of chips

Micro-data-loggers are miniature autonomous systems intended to measure and memorize various physical parameters during a period of up to a few months or years. It is proposed that such devices be composed of only three main chips: a general management chip, a measurement chip, and a storage memory. The micro-data-loggers' context (including micropower) is discussed, and the main characteristics that such components must exhibit are described. The management chip has been realized and tested. The proposed structure of the measurement chip is based on the experience gained with several micro-data-loggers realized with standard components. The emphasis is on the programmability of the chips, which allows a broad range of applications     

Cleavage Fracture of Brittle Semiconductors from the Nanometre to the Centimetre Scale

The objective of this paper is to present the fundamental phenomena occurring during the scribing and subsequent fracturing process usually performed when preparing surfaces of brittle semiconductors. In the first part, an overview of nano‐scratching experiments of different semiconductor surfaces (InP, Si and GaAs) is given. It is shown how phase transformation can occur in Si under a diamond tip, how single dislocations can be induced in InP wafers and how higher scratching load of GaAs wafer leads to the apparition of a crack network below the surface. A nano‐scratching device, inside a scanning electron microscope (SEM), has been used to observe how spalling (crack and detachment of chips) and/or ductile formation of chips may happen at the semiconductor surface. In the second part cleavage experiments are described. The breaking load of thin GaAs (100) wafers is directly related to the presence of initial sharp cracks induced by scratching. By performing finite element modelling (FEM) of samples under specific loading conditions, it is found that the depth of the median crack below the scratch determines quantitatively the onset of crack propagation. By carefully controlling the position and measuring the force during the cleavage, it is demonstrated that crack propagation through a wafer can be controlled. Besides, the influence of the loading configuration on crack propagation and on the cleaved surface quality is explained.     

Determining adhesion and hermeticity of the interface between encapsulation polymer and insulating layer of micro-sensing chips via a capacitance-voltage technique

The successful application of micro-sensing chips based on ion-sensitive field effect transistor principles depends on preventing the penetration of electrolyte into the interface between the encapsulation polymer and the insulating layer. This study employs a capacitance-voltage (C-V) technique to evaluate the adhesion and hermeticity of the polymer-substrate interface in a liquid environment. Three-layered structures simulating micro-sensing chips were fabricated for the evaluation. Each three-layered structure comprises an upper epoxy layer (with or without a window opening), a middle dielectric layer, and a lower Si wafer substrate. Equivalent circuits were established to explain the C-V characteristics of the three-layered structures. The results show that by applying the C-V technique and using an appropriate equivalent circuit, the adhesion and hermeticity between the encapsulating epoxy layer and the insulating layer can be evaluated.     

A model-based clustering approach to the recognition of the spatial defect patterns produced during semiconductor fabrication

Defects on semiconductor wafers tend to cluster and the spatial defect patterns of these defect clusters contain valuable information about potential problems in the manufacturing processes. This study proposes a model-based clustering algorithm for automatic spatial defect recognition on semiconductor wafers. A mixture model is proposed to model the distributions of defects on wafer surfaces. The proposed algorithm can find the number of defect clusters and identify the pattern of each cluster automatically. It is capable of detecting defect clusters with linear patterns, curvilinear patterns and ellipsoidal patterns. Promising results have been obtained from simulation studies.