MOS voltage reference based on polysilicon gate work function difference

A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

一种工作在亚阈值区的低电压低功耗基准电压电路

本文提出了一种不使用三极管而只使用工作在亚阈值区的晶体管和电阻的电压基准。使用0.18um工艺进行流片以及测试的结果表明：本文所设计的电压基准可在0.8V的低电压下工作,在温度从-35˚C到85˚C的范围内,温度系数为370ppm/˚C;电源电压从0.8V到3V的条件下,电压偏差小于0.1%。而且在电源电压为0.8V的条件下,整个芯片的功耗只有1.5uA。     

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

标准CMOS工艺栅控Si-LED设计与制备

采用新加坡半导体制备有限公司的0.35um EEPROM双栅标准CMOS工艺设计和制备了U型Si-LED发光器件。器件结构采用P+-N+-P+-P+-P+-N+-P+-P+-P+-N+-P+叉指结构形成U型器件,外部的两个P+区为保护环,在相邻的内部两个P+区之间使用多晶硅作为栅极来调控LED的正偏发光。使用奥林巴斯IC显示镜测得了硅LED实际器件的显微图形,并对器件进行了电学的正反向I-V特性测量。器件在室温下正向偏置,在100～140mA电流下对器件进行了光功率的检测,发光峰值在1089nm处。结果表明,器件发光功率随着栅控电压偏置电流的增加而增加。     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

CMOS传输门工作特性的Multisim分析

针对CMOS传输门工作特性的实验验证,提出了在计算机上应用Multisim仿真软件仿真CMOS传输门传输特性的方法,即用Multisim软件中的函数发生器提供正弦信号、三角信号和脉冲数字信号,用虚拟仪器中的双踪示波器显示输入信号、输出信号的波形。特点是直观形象地描述了CMOS传输门的功能和工作特性、解决了CMOS传输门工作波形无法用电子实验仪器进行分析验证的问题。     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (V_{B , V} ) on impurity concentration (N_d ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy ε_T in the electron, a new formula of silicon critical electric field E_{S , C} on N_d is derived by solving a 2D Poisson equation, which increases with the increase in N_d especially at higher impurity concentration, and reaches up to 68.8?V/µm with N_d  = 1 × 10¹⁷?cm^?3 and 157.2?V/µm with N_d  = 1 × 10¹⁸?cm^?3 from the conventional about 30?V/µm, respectively. A new physical concept of critical energy ε_B is introduced to explain the mechanism of variable high E_{S , C} with heavy impurity concentration. From the E_{S , C} , the expression of V_{B , V} is obtained, which is improved with the increasing N_d due to the enhanced E_{S , C}. V_{B , V} with a dielectric buried layer thickness (t_I ) of 2?µm increases from 428?V of 1 × 10¹⁷?cm^?3 to 951?V of 1 × 10¹⁸?cm^?3. The dependence of N_d and top silicon layer thickness (t_S ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.     

Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride

A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G/sub M/) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G/sub M/ of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G/sub M/ further to 29% more than the single-poly-Si gate structure without SiN capping layer.     

Fully integrated dual-band VCOs with power controlled by body voltage in 130 nm CMOS/SOI for multi-standard applications

In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are 5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were −89 and −93 dBc/Hz at 5.2 and 3.6 GHz respectively.     

A temperature-stabilized SOI voltage reference based on thresholdvoltage difference between enhancement and depletion NMOSFET's

A temperature-stabilized silicon-on-insulator (SOI) voltage reference is presented. It is based on the threshold voltage difference between enhancement and depletion SOI NMOSFETs that have the same channel doping concentration but of opposite type. The circuit has been realized on a SIMOX wafer using an n⁺-poly gate and a LOCOS isolation process. The threshold voltages of the enhancement and depletion SOI NMOSFETs show almost the same temperature dependence when a suitable back-gate bias is applied. Experimental results show a temperature coefficient of 33.8 p.p.m./°C over the temperature range of -50 to 75°C. The variation of threshold voltage difference with temperature is small, and this circuit becomes more advantageous as the front-gate oxide is scaled down or the bias current is reduced     

Measurement of the mobility and concentration of carriers in diffused zones in Si with a gate controlled structure

A gate controlled structure is described. It is shown to be a convenient device for measuring mobility and concentration profile of majority carriers in diffused zones. The values of these two parameters are derived from measurements of gate capacitance and resistivity as a function of gate voltage. Various ways of obtaining C-V deep-depletion curves are discussed in order to justify the choice of a gate controlled structure. The measurement technique is discussed. Limitations of the method are due, on one hand, to the depletion approximation and, on the other hand, to an excessive reverse current across the diffused junction induced by the gate voltage. This effect is encountered especially in low-concentration samples, such as ours, in the range of 10¹⁵-10¹⁶cm^-3. For illustration purposes, profiles of a p diffusion used in the MOSC process are measured at the beginning and at the end of the fabrication process.