一种256k动态随机存取存贮器

本文介绍一种采用冗余技术的5伏电源电压工作的256k×1位NMOS动态RAM。这种存器使用2.3微米设计规则,存贮单元设计为叠式位线结构,其行节距为6.5微米,读出放大器节距为18微米;硅化钽/多晶硅结构用作第二层多晶硅层,以减少行钱时间常数;存贮电容为60fF,而且采用HiC单元结构,这样使得存贮器具有很好的抗α粒子特性;管芯尺寸为4.66×11.65毫米,采用标准的0.3英寸(7.62毫米)厚的16腿双列直插式管壳封装。这种存贮器以256刷新周期工作,刷新时间为4毫秒;典型的RE/CE存取时间为105/65毫米微秒;工作功耗为250毫瓦,典型的维持功耗小于20毫瓦;这种存贮器与西方电气公司现有的5伏64k存贮器兼容。     

1兆位动态随机存取存贮器

东芝公司研制成功1兆位动态随机存取存贮器,芯片面积为4.78×13.23毫米,集成了225万个晶体管和电容器,结构为1,048,576字×1位,双列直插式封装.该器件采用了埋入氧化物隔离方法,存贮器单元为5×6.4微米,这有助于在每个单元写入或读出时稳定而无误差地工作.工作功耗为270毫瓦,响应时     

容错64K动态随机存储器

64K动态随机存储器设计要考虑的几个主要问题是:(1)与16K产品的相容性;(2)提供足够强度的读出信号,(3)电流峰值与平均值降到最低;(4)可高成品率制备。本文讨论了上述诸因素的影响,存储器结构以及电路设计等问题。     

64K存贮器开发年表

64K存贮器开发年表年. 份1975年2月1976年3月1977年4月1977年8月i978年2月1978年2月1.978年4月1978年4月1978年5月1978年9月1978年lO月1978年12月197睥12月1979年2月1980年2月1980年夏?日本电电公社开始超大规模集成电路研究三年计划;日本超大规模集成电路研究组合开始四年计划?日本电电公社报导试制成功64K存贮器j日本电电公社攀表64 K存贮器试制报告 :j曼查皇皂釜社和西德西门子公司在国际固体电路会议上报导64K存贮;器试制情况 。 。一………………‘“～}日本富士谭/公司宣布64K存贮器达到产品化水平j.{美国英特尔公司提出软误差问题…     

64K位VMOS随机存取存贮器

本文将叙述一种根据早期试验器件的经验设计的64K位动态随机存取存贮器,其取数时间为150ns。器件芯片面积为3.6×7.0mm~2=25.2mm~2,装配在16条腿的管壳内。其电源为+8V和-2.5V;所有输入输出端皆与TTL相容。 芯片的显微照片如图(1)所示,它示出了芯片的内部结构:存贮单元陈列所占面积大于整个芯片的50％,由位译码器对等地分为两部分。取决于所加地址,启动包括读出放大器在内的一半单元。     

P沟硅栅等平面256位动态随机存贮器设计总结报告

打倒了“四人帮”我国电子工业的发展进入了新时期,特别是电子计算技术的迅猛发展对新型的半导体存储器的研制提出了迫切的要求。为了配合我省微小型计算机的研制,我们结合74届学员的毕业设计,在南京无线电研究所进行了P沟硅等平面256位MOS动态机存储器的设计试制工作。 在设计时我们的指导思想是:（1）尽量利用南厅MOS工艺的已有条件,力争在半年毕业设计时间中完成设计试制工作,以期达到既出产品又出人才的目的;（2）优先考虑电路的稳定性和可靠性,然后争取有较好的其他性能;（3）积累经验,为今后设计研制更先进的沟硅存储器等新产品创造条件。 在设计方案上我们考虑了如下几点:（1）采用P沟栅等平面工艺,因为P沟工艺较成熟,易做出结果,硅栅工艺有利于缩小芯片面积和提高速度,等平面工艺有利于提高成品率;（2）采用器管动态单元、以期提高电路的可靠性和稳定性;降低电路功耗,同时采用了译码器接地管和驱动器自电路,目的亦是为了降低功耗和提高速度。电路概况如下:电路特点:动态器管单元工艺特点:P沟硅栅等平面电路结构:256字×1位芯片面积:2.5mm×2.5mm（包括压焊块） 2mm×2mm（不包括压焊块）电路框见（1.1）芯片中集成了:16×16=256个存储单元x地址反相器 A_0～A_3（共4只）     

64K动态存贮器用的基本工艺技术

64K动态存贮器用的基本工艺技术 。 光刻技术{凳娄袭蕞剂 ;篓茬竺耋磊等倍投影曝光 腐蚀技术 {湿法腐蚀一同时采用等离子千法腐蚀 元件间隔离技术 j选择氧化法 栅氧化技术 i干氧氧化法栅电极技术扩散层形成技术层间绝缘膜形成技术金属布线材料单层多晶硅一双层多晶硅热扩散法一全离子注入法回流技术一层铝64K动态存贮器用的基本工艺技术@黄子伦     

N沟硅栅MOS单管单元4096位动态随机存取存贮器(RAM)

n沟硅栅MOS单管单元4096位动态随机存取存贮器,采用当前最广泛的n沟硅栅工艺制造。在不太严格的工艺条件下,即位线宽度7.5微米,位线电容C_D与单元电容C_s比等于或大于10的情况下,设计了一种读出放大器,使之能读出200毫伏左右的信号。单元的面积是60×30微米~2,芯片的总面积为4×5毫米~2。     

64M闪速存贮器K9K1208UOM及其应用

K9K1208UOM是SAMSUNG公司生产的大容量非易失性闪速存贮器,本文介绍了K9K1208UMO的性能、结构、工作原理,并重点介绍了该闪速存储器的使用方法,最后给出了K9K1208UOM的各状态寄存器的定义和命令集。     

Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node

Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits     

Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories

Conventional memory address decoders based on static CMOS gates incur high clock loading and unnecessary power dissipation in unselected banks. This paper presents a dynamic word line decoder which is fast, has reduced active and leakage power dissipation, and also enables faster race-free sense timing. In a multi-bank memory array with sixteen decoders, the energy–delay product of the dynamic decoder is 66% lower than a low-power static version. The design leverages the predictability of dynamic circuits to provide significant decoder leakage reduction in unselected banks. The dynamic decoder has been fabricated on a 90 nm bulk CMOS process. The measured test chip address to word line delay is 170 ps at 1.5 V and the measured leakage reduction is over 20x at $V_{rm DD}$ greater than 0.8 V.      

Review and Perspective of Architecture Development for Dynamic Random Access Memory

Discussed is a review and perspective of architecture, materials and process technology for dynamic random access memory（DRAM） applications. Key challenges of the transistor and capacitor scaling from DRAM will be reviewed. To continue scaling down, multi-gate devices with very thin silicon channels are most promising. Several architectures like Fin-field effect transistor（Fin-FET）, Wafer bonded double gate and silicon on nothing（SON） gate-all-around have been demonstrated with good electrical characteristics. An overview of the evolution of capacitor technology is also presented from the early days of planar poly/insulator/ silicon（PIS） capacitors to the metal/insulator/metal（MIM） capacitors used for today 50 nm technology node and below. In comparing Ta2O5 , HfO2 and Al2 O3 as high-k dielectric for use in DRAM technology, Al2 O3 is found to give a good compromise between capacitor performance and manufacturability used in MIM architecture.     

Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory

Body effect is a key characteristic of a dynamic random access memory (DRAM) cell transistor. The conventional method uses a test element structure or nano-probe equipment for body effect measurements. However, the test element structure measurement is inaccurate because the structure is located outside the DRAM chip. Additionally, the nano-probe destroys the chip while measuring the body effect in the chip. Therefore, we developed a novel nondestructive method to measure the body effect in the DRAM. This method uses a memory bitmap test system. The test system was originally a device that determines pass or fail of the cells. However, it was modified to extract the gate voltage that causes the failure due to a cell transistor leakage current. Because the leakage current is correlated to the threshold voltage, this gate voltage is a relative threshold voltage. The body effect was obtained by measuring the relative threshold voltage under different body biases. After confirming the method in a single cell, we simplified the method for a mass cell measurement. Two relative threshold voltages for each body bias were used for a fast and simple test. The mass measurement method could obtain 8196 body cell effects within 2 min. The results of the newly developed method were the same as that of the conventional test element structure measurement.     

Refinement of Unified Random Access Memory

This paper investigates how gate height $(H_{g})$, which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower $H_{g}$ yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower $H_{g}$ shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.      

基于FRAM铁电存储器的可移动数据采集器

使用新一代的非易失性存储器棗铁电随机存取存储器,设计一种能长时间记录变化缓慢的直流信号或监测捕捉记录偶尔出现的脉动信号的可移动数据采集器,是低成本解决现场数据的自动记录的有效办法。文章介绍了几种简单易行的数据记录方法和用Ramtron公司生产的FM24C256存储芯片设计的可移动数据采集器及其记录程序流程,给出了一种可变采样频率记录和脉冲检测记录的综合记录方式数据采集器设计方法。     

电磁故障注入攻击对动态随机存取存储器安全性的影响研究

以探索电磁故障注入(EMFI)攻击对动态随机存取存储器(DRAM)的安全性影响为目标,该文使用电磁故障注入攻击平台对DRAM进行了扫描攻击,对出现的故障进行统计分类,随后基于DRAM的基本结构分析阐述了造成故障的机理,最后展示了通过电磁脉冲攻击DRAM对计算机系统的安全威胁.实验表明电磁脉冲在DRAM中既可以引起瞬时故...     

电磁故障注入攻击对动态随机存取存储器安全性的影响研究

以探索电磁故障注入(EMFI)攻击对动态随机存取存储器(DRAM)的安全性影响为目标,该文使用电磁故障注入攻击平台对DRAM进行了扫描攻击,对出现的故障进行统计分类,随后基于DRAM的基本结构分析阐述了造成故障的机理,最后展示了通过电磁脉冲攻击DRAM对计算机系统的安全威胁.实验表明电磁脉冲在DRAM中既可以引起瞬时故障也可以引起持续性故障,且以多故障为主.分析发现,电磁脉冲故障攻击技术可以以低的时间和空间分辨率向DRAM的指定地址注入持续性故障.另外,该文成功地将持续性故障注入到了存储在DRAM中的AES-128程序中并破解了其密钥,证明了使用电磁脉冲对DRAM进行攻击能对计算机系统造成安全威胁,展示了DRAM安全性的研究对硬件系统安全具有重要意义.     

Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic CMOS process

One of the promising technologies under development for next generation non-volatile memory is the Conductive Bridging Random Access Memory (CBRAM) which utilizes the reversible switching of an electro-resistive dielectric between two conductive states as means of storing logical data [1], [2], [3], [4], [5], [6] and [7]. In this paper, we describe the successful integration of CBRAM technology into an industry standard logic process. Moreover, we show functional operation of such a fully CMOS integrated CBRAM memory array and highlight its specific fundamental low power characteristics that make it suitable to be used in scaled embedded application as well as discrete devices.     

非易失性静态随机存储器研究进展

在非易失性存储器领域,非易失性静态随机存储器(NVSRAM)可以克服现有非易失性存储器的缺点与限制,并完全替代静态随机存储器(SRAM)。首先,对几种新型非易失性存储器进行了简单阐述;其次介绍了NVSRAM的基本工作原理和特点,针对NVSRAM在解决传统SRAM掉电数据储存问题、加快读取速度以及减少功耗等方面的优势进行阐述。对近年来基于阻变存储器的NVSRAM的研究背景和国内外研究现状进行了调研,着重比较和分析了已有结构的优缺点,重点探讨了提高恢复率、减少漏电流和降低功耗的关键优化技术。最后,展望了NVSRAM未来的应用和研究发展方向。