Voltage acceleration of time-dependent breakdown of ultra-thin gate dielectrics

Experimental results support the power-law model to correctly describe the voltage acceleration of time-dependent dielectric breakdown (TDDB) in an oxide thickness range where direct tunnelling of electrons is the primary leakage mechanism. The accessible experimental time range to prove a certain voltage acceleration behaviour is compared to the time range that needs to be covered during a projection to use conditions. Further, the problem of correct gate oxide breakdown detection in PFET devices is discussed, because it strongly affects the determination of time to breakdown, Weibull slope, acceleration model, and acceleration factor.     

Empirical BEOL-TDDB evaluation based on I(t)-trace analysis

In this paper we are proposing a comprehensive approach of analyzing I(t)-traces generated during BEOL-TDDB (Time Dependent Dielectric Breakdown) investigations. The relations of the initial leakage, the shape of the I(t)-trace and the voltage dependence of the components are discussed. Clear voltage and area dependence could be found. The TDDB lifetime itself and also the transition point of the two I(t)-trace components describes the TDDB voltage acceleration very well. Additionally the review of the breakdown charge gives evidence that only one component is responsible for the TDDB breakdown behavior.This empirical evaluation delivers a different view on the I(t)-trace shapes leading to better understanding of its contributions to the TDDB behavior.     

Field Acceleration Model for TDDB: Still a Valid Tool to Study the Reliability of Thick SiO2-Based Dielectric Layers?

The aim of this paper is to investigate the reliability of thick oxides that are dedicated to the power integrated device fabrication. The field dependence of defect-related time-dependent dielectric breakdown (TDDB) mode over a wide range of oxide thickness T_OX and electric field E, using multiple wafer fabrication lots, is investigated. TDDB tests are conducted under constant current injection using structures with different areas. For that, we have applied a new electric field model based on a 1/E model (reciprocal field dependence) that is proposed recently in the literature. We show that when the dielectric thickness increases, this electric field acceleration model gives an erroneous prediction of the long-term reliability. We conclude that it is too early to give a generalized law of dielectric to predict their reliability without taking into account the influence of thicknesses. Consequently, the 1/E model may therefore have to be revised.     

Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

In this work, the effects of voltage and temperature on the TDDB characteristics of 2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (t_BD) are recorded from p⁺-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The t_BD cumulative distributions exhibit a single Weibull slope β of 1.9 for different applied voltages. The charge-to-breakdown (Q_BD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm² on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of 14.83 V⁻¹. It is projected that the maximum safe operating voltage is 1.9 V for 2.07 nm O/N gate dielectric.     

On the optimum thickness to test dielectric reliability, in an integrated technology of power devices

This paper deals with the extensive characterization of dielectric films with thicknesses from 20 to 65 nm. Thick dielectric reliability has been investigated with time dependent dielectric breakdown (TDDB). TDDB tests are conducted under constant current injection. Assuming that the logarithm of the median time-to-failure is described by a linear electric field dependence, a generalized empirical law for the long-term reliability of the dielectric is proposed. This law takes into account the applied electric field and the dielectric thickness. This reliability law is available for dielectric thicknesses greater than 10 nm. A procedure to test dielectrics of various thicknesses is given in order to predict their reliability in power integrated devices.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Electron fluence driven,Cu catalyzed,interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.     

薄栅介质TDDB效应

在恒压和恒流应力条件下测试了超薄栅氧化层的击穿特性 ,研究了 TDDB(Tim e Dependent DielectricBreakdown)的可靠性表征方法 .对相关击穿电荷量 QBD进行了实验测试和分析 .结果表明 :相关击穿电荷量 QBD除了与氧化层质量有关外 ,还与应力电压和应力电流密度以及栅氧化层面积有关 .对相关系数进行了拟合 ,给出了 QBD的解析表达式 .按照上述表达式外推的结果和实验值取得了很好的一致 .提出了薄栅介质 TDDB效应的表征新方法     

Stress voltage polarity dependence of thermally grown thin gateoxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO₂ films in a polycrystalline silicon-SiO₂-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm² constant current with positive and negative voltages at 250°C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film     

Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (t_BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.     

Physical model for the power-law voltage and current acceleration of TDDB

As gate voltages scale in ultra-thin gate oxide CMOS and single carrier energy drops below the threshold required for defect generation, we postulate that multiple carrier induced defect generation becomes the dominant degradation mechanism resulting in a power-law voltage and local current acceleration of time-dependent dielectric breakdown (TDDB). Data from multiple technology nodes is presented to corroborate our hypothesis, which is also demonstrated to be consistent with literature reports from several different companies. To the best of our knowledge, this is the first time the power-law local gate current acceleration is proposed in contrast to earlier formulations based on total gate current.     

Static and dynamic hot carrier accelerated TDDB: Influencing factors and impact on product lifetime

In this paper we show the full picture of hot carrier accelerated TDDB from static single transistor tests to AC stress and finally, to real product assessments. The different influencing factors like voltage, temperature and Vth are shown to be similar for all stress types. Moreover, an AC frequency dependency – that can be explained by the considerable lifetime of hot carriers – results in a further reduction of the breakdown time. The field relevance is assessed by long term (4000 h) HTOL product tests.     

Time dependent dielectric wearout (TDDW) technique for reliabilityof ultrathin gate oxides

The degradation of ultrathin oxides is measured and characterized by the dual voltage time dependent dielectric wearout (TDDW) technique. Compared to the conventional time-dependent dielectric breakdown (TDDB) technique, a distinct breakdown can be determined at the operating voltage I-t curve. A noisy, soft prebreakdown effect occurs for 1.8-2.7 nm ultrathin oxides at earlier stress times. The different stages of wearout of 1.8-2.7 nm oxides are discussed. The wearout of oxide is defined when the gate current reaches a critical current density at the circuit operating voltage. Devices still function after the soft breakdowns occur, but are not functional after the sharp breakdown. However, application of the E model to project the dielectric lifetime shows that this is more than 20 y for thermal oxides in the ultrathin regime down to 1.8 nm     

Reliability of ultra thin ZrO2 films on strained-Si

Ultra thin high-k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers using zirconium tetra-tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO₂ gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO₂ is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO₂ layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. The trapping charge density, Q_ot and charge centroid, X_t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd > 1500 s) is observed under high constant voltage stress.     

Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

Assessment of temperature and voltage accelerating factors for 2.3–3.2 nm SiO2 thin oxides stressed to hard breakdown

The temperature and voltage acceleration for a large database of time dependent dielectric breakdown in 2.3 and 3.2 nm SiO₂ oxides is investigated. All results deal with the time to hard breakdown which is defined when a typical high current limit (1 mA) at operating voltage is reached rather than detecting the first current change as is conventionally done. Using an accurate experimental error evaluation, long range data are compared for consistency to the predictions of various state-of-the-art extrapolation models used to qualify these oxides, to point out which one describes the data best. The activation energies corresponding to the dominant degradation mechanisms are extracted over a temperature range from 50 °C to 125 °C for N type substrate stressed in accumulation regime. The voltage extrapolation models are compared for P and N type substrate with positive stress polarity on the gate. It is verified that a TDDB power voltage law is well predictive for both P substrate in inversion regime and N substrate in accumulation regime.     

Charge to breakdown mechanism of thin ONO films

Effects of charge trapping in the thin ONO (oxide silicon nitride oxide) film caused by the voltage stress on the time-dependent dielectric breakdown (TDDB) mechanism are studied. The purpose is to report the TDDB data of the films after various treatments of charge injection and thermal annealing together with analysis of the experimental data to enhance the understanding of the dielectric breakdown mechanisms of the ONO film. It is observed that the trapped charges injected from one electrode have very little effect on the TDDB mechanism during stress to the other electrode. This suggests that the position of trapped charges may be quite different for the two injecting electrodes and that breakdown mechanisms may be initiated from the different charge positions and sources     

Voltage acceleration and t63.2 of 1.6–10 nm gate oxides

Gate oxide reliability data collected over a considerable period of time were compiled to assess the voltage acceleration and the time to breakdown as function of oxide thickness. These data cover a range from 1.6 to 10 nm and can be used as benchmark for technologies that are still using gate oxide in this thickness range. The data form well-defined bands for each of the voltage acceleration models. The functional dependence of the parameter on oxide thickness depends strongly on the voltage acceleration model. The accuracy of the voltage acceleration parameters determined for the different acceleration models is studied. The time to breakdown at one voltage spans many time-decades if the data covering the entire thickness range are plotted in one graph. Therefore, the use of a model-free value, the voltage to get 63.2% breakdown at a certain fixed time, is proposed for plotting the data taken in the wide oxide thicknesses range, instead of normalizing the time to breakdown to a certain voltage using one of the voltage acceleration models. Based on the results a self-consistent test of the voltage acceleration models is introduced. This parameter also supports the t_bd power law and therefore the hydrogen release model when plotting the voltage acceleration parameter of the exp(V)-model versus the inverse model-free gate voltage to get 63.2% breakdown at a fixed time.