Weak inversion charge injection in analog MOS switches

The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor     

Measurement and analysis of charge injection in MOS analog switches

The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.     

Charge injection in analog MOS switches

Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.     

A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

Measurement and modeling of charge feedthrough in n-channel MOS analog switches

Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed. A first-order computer simulation based on the quasi-static small-signal MOSFET capacitances shows good agreement with experimental results.     

A simplified and efficient numerical model for charge injection inacoustic charge transport devices

A numerically efficient model for simulating electrical charge injection in acoustic charge transport (ACT) devices is developed. This model simplifies an existing charge injection model and is derived using the coupled set of semiconductor device equations. The present model increases the computational efficiency of decoupling and reducing the number of mathematical equations forming the charge injection model. A brief overview of the original model is presented. The assumptions leading to the decoupling and reduction of the device equations are described, as are differences between the two models. Results computed by the simplified model are shown and compared to the results from the original charge injection model and experimental measurement. The present model is able to examine 45 SAW wave positions and 163 contact voltages in 8 h on a 25 MHz PC in comparison to the previous model which simulated 59 wave positions and 164 contact voltages on an Hewlett-Packard 9000 series 500 minicomputer in 37 h. A substantial reduction in computation time is achieved     

A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

A new charge conserving capacitance model for GaAs MESFET's

We present a new charge conserving capacitance model for Gallium-Arsenide (GaAs) metal semiconductor field effect transistors (MESFET's) based on the quasi-static approximation and a proper partitioning of the channel charge between the source and the drain terminals. A total of nine so-called transcapacitances were determined by taking derivatives of the various terminal charges with respect to the voltages at source, drain, and gate. The transcapacitances are nonreciprocal, i.e., C_ij≠C_ji when i≠j, and can be organized in a 3×3 matrix incorporating Kirchhoff's current law (charge conservation) and independence of reference. The present capacitance model is valid both above and below threshold, and shows good agreement with experimental data over a wide range of gate and drain biases. The model is analytical and suitable for implementation in circuit simulators     

An analytical model for charge pumping below strong inversion and accumulation

A compact analytical model for charge pumping (CP) is derived. It accounts for emission during the high and low gate bias levels and assumes instantaneous transition edges. This model, which does not apply on the top of the CP curves when using large gate voltage swings, where emission fully proceeds during the transitions edges of the gate signal, applies on all the other regions provided that the transition times of the gate signal are much shorter than the times at steady state biases. Therefore it holds at large bias swings on both edges of Elliot curves and at small bias swings on the whole Elliot curves provided that the interface traps are completely filled [1]. It is compared with the analytical model proposed by Wachnik and Lowney [2] in which emission is not accounted for at all. This model, which holds at Elliot curve maxima when small voltage swings are used, has been shown to be extremely useful for studying interface trap properties [1, 2, 3 and 4]. The CP model proposed primarily, that of Brugler and Jespers [5], is used as a reference. The model derived in this article very satisfactorily fits the experimental curves in the regions of large CP current where it holds. Discrepancies at low current levels are due to the well-known contribution of the transistor source and drain regions or could be due to edge effects. Comparing the different models and the experimental curves allows to evaluate emission and capture during different regions of the gate bias period. The three regions of CP response, depending on the gate voltage swing and involving or not emission and the full filling of the interface traps, are also evidenced.     

A new technique for analog multiplication

Describes a new method using emitter current crowding for performing accurate multiplication of analog signals using devices of special geometry but capable of fabrication with a standard bipolar process. A narrow region of current injection-a carrier domain-can be positioned on an emitter by one electrical input and controlled in magnitude by a second input. The resistive epi layer resolves this current into a differential output proportional to the product of the inputs. A key advantage of these multipliers is their low noise. The basic principle can be applied to many other nonlinear operations. A two-quadrant and a four-quadrant multiplier are described.     

A new MOS-gate bipolar transistor for power switches

A new monolithic integrated power device, the MOS-gate transistor (MGT), which consists of a bipolar transistor for an output stage and two MOSFET's for a driver stage, has been investigated. The purpose of the study was to obtain a power switch having characteristics of an easy drive, a short turn-off time, and a high current density. The developed device structure featured the integration of three elements into a small cell from a large number of which the MGT chip was constructed. This device had no parasitic thyristor, making it free from the latchup phenomenon. Unit MGT devices with a blocking voltage of 400-500 V were fabricated. A high current density of 90 A/cm²at a collector-emitter voltage of 2 V and a short turn-off time of less than 1 µs were obtained. The MGT devices, which contained 36 cells, were fabricated with chip sizes of 5 × 5 mm. They exhibited a blocking voltage of 500 V, on-state voltage of 2.3 V at a current of 10 A, and turn-off time of 0.5 µs at 150°C.     

Numerical model for electrical charge injection in the acousticcharge-transport device

A two dimensional model is developed to study the electrical charge injection process at the input of a GaAs buried-channel acoustic charge-transport device. The model allows for nonuniform impurity doping profiles, variable epitaxial layer configurations, and arbitrary structural designs of the input electrode architecture. The acoustic wave potential is incorporated as a time- and space-varying doping density that adds directly to the impurity doping density. The wave-induced doping density is obtained from the piezoelectric displacement charge that accompanies the acoustic wave. The partial differential equations which form the mathematical basis of the charge injection process are derived from the semiconductor transport equations and solved numerically. The algorithm for simulating charge injection and the results of a simulation are presented. This model provides a means for characterizing the electrical performance of the acoustic charge-transport device input circuit in terms of device physics     

A biochemical translinear principle with weak inversion ISFETs

A weak inversion region is shown to exist in ion-sensitive field effect transistor (ISFET) sensors. It is therefore proposed that the ISFET and its chemically sensitive (ChemFET) counterparts be used as translinear elements in the synthesis of novel biochemical input stages which perform real-time mathematical manipulation of biochemical signals. A Biochemical Translinear Principle using weakly inverted ChemFETs is presented. A low-power current-mode input stage circuit is presented as an application of the principle. This yields a linear relation between drain current and hydrogen ion concentration valid over four decades. This paper demonstrates an important and necessary step toward biochemical VLSI.     

A new queuing strategy for large scale ATM switches

In this article, different buffering techniques used to solve the contention problem in ATM switching architectures are compared. Then, the buffer requirements needed to achieve a given quality of service (QoS) is determined. Based on the results, we propose a combined central and output queuing (CCOQ) technique to be used in designing large-scale ATM switches for high-speed networks     

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.     

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

A new self-align technology for GaAs analog MMIC's

A new self-align technology suitable for fabrication of GaAs low-noise FET's and MMIC's is demonstrated. The present technology, which is based upon sidewall technology and pattern inversion technology, provides a negligible short-channel effect, a low-parasitic resistance and a well-controlled breakdown voltage, all of which are essentially required for high microwave performance. An experimental 0.5-µm gate FET fabricated using the new process exhibits a high transconductance such as 220 mS/mm and a low-noise figure such as 1.6 dB at 12 GHz.     

Digital signal processing spectrum inversion for analog speech channels

Speech security communication systems applied to radio analog speech channels become more and more desirable as radio channel capacity increases and service area spreads. Analog spectrum inversion used in existing radio communication systems is suitable for preventing eavesdropping and ensuring security, but it suffers from inevitable speech quality degradations. It is shown that digital spectrum inversion can be accomplished merely by alternating the sign of the sampled data to avoid distortion. Digital inversion is theoretically deduced by the discrete Fourier transform and verified by experiments. The aperture effect is also discussed from the viewpoint of spectrum inversion. Digital spectrum inversion is implemented with exclusive OR gates and a one digit binary counter, which is easily integrated onto a large scale integration (LSI) chip to avoid element value deviation. Signal-to-noise ratio (SNR) and distortion are observed to be more than 50 dB and -50 dB right across the 0.3-3.7 kHz frequency band, when an 8 kHz sampling rate is adopted for digital processing.