Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Adhesion and toughening mechanisms at underfill interfaces forflip-chip-on-organic-substrate packaging

The flip chip-on-organic-substrate packaging technology utilizes a particulate reinforced epoxy as the underfill (UF) to adhere the chip to the package or board, Although the use of underfill encapsulation leads to improved reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major concern for assembly yield loss and package reliability. In spite of their importance, the adhesion and fracture behaviors of the underfill interfaces have not been investigated until recently. Considerable controversy exists over the effects of underfill formulation and the adhesion and toughening mechanisms of the interfaces. The present work focuses on investigating the effects of several key variables on the interface adhesion strengths for UF/chip and UF/organic substrate systems. These variables are underfill organosilane content, filler particle content, rubber particle content, surface morphology and chemistry of the chip and organic substrates. The approach of this study is to measure the effect of these variables on the interfacial fracture energy using the double-cantilever-beam (DCB) techniques. The results demonstrate that the underfill interfacial adhesion and fracture characteristics are controlled by several distinct but competing mechanisms, such as formation of primary bonds, crack-pinning by glass fillers, debonding of glass filler from epoxy matrix (defect formation), and cavitation and shearing induced by rubber particles. Fundamental understanding of the interfacial adhesion and toughening mechanisms can provide guidance for developing new processes and materials to enhance interfacial adhesion and reliability     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Determination of Fracture Toughness of Underfill/Chip Interface With Digital Image Speckle Correlation Technique

The layered packages are prone to multimode damages and failures when they are subjected to complicated and coupling environmental loading. As a result, fracture toughness is usually used as a fracture criterion to evaluate the reliability of polymer/inorganic interface. In this study, an in-situ/real-time micro-digital image speckle correlation (mu-DiSC) system was established and employed to determine the fracture toughness of underfill/chip interface involved in flip chip assembly. The tests were carried out over a wide range of temperatures and at various loading angles. In order to verify the finding of the mu-DiSC technique, an interface fracture mechanics based finite element model is implemented into ANSYS to calculate the values of crack-tip opening displacement of underfill/chip joint under different loading configurations. The results obtained from the simulation are found to be in good agreement with those measured by the mu-DiSC system, indicating that the system can be used as an accurate and effective experimental tool for the electronic packages. The fractographs, with respect to different temperatures and loading angles, are further discussed     

倒装芯片下填充工艺的新进展(二)

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

倒装芯片下填充工艺的新进展(一)

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

Die stress characterization in flip chip on laminate assemblies

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150/spl deg/C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.     

Measurement of underfill interfacial and bulk fracture toughness in flip-chip packages

Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Adhesion measurement for electronic packaging applications usingdouble cantilever beam method

Multilayers and interfaces are ubiquitous in microelectronics devices, interconnect and packaging structures. As the interface integrity becomes the major concern of performance, yield, and reliability, the need to evaluate the fracture and delamination behavior of various interfaces increases. This work focused on quantifying interfacial adhesion performance of a typical electronics packaging structure, flip-chip-on-organic-substrate. A series of experiments and analyzes were conducted to investigate the adhesion and fracture behaviors of the underfill/silicon and underfill/organic substrate interfaces. The experimental techniques for the interfacial fracture experiments were developed to produce the double-cantilever-beam (DCB) specimens and to establish a reproducible testing protocol. To extract the interfacial fracture energies, a closed-form solution was developed based on a beam-on-elastic-foundation model. A two-dimensional elastoplastic finite element analysis (FEA) model was also implemented to examine effects of mode-mixity, thermal/residual stresses, and underfill plasticity. The techniques allow for reproducible determination of underfill/printed circuit board (PCB) and underfill/silicon chip interfacial adhesion strength. The developed techniques are also readily applicable to evaluate interfacial adhesion performance for many other similar electronic packaging systems. This provides capabilities in optimizing material selections and process conditions to improve interfacial adhesion performance, Additionally, the interfacial fracture energy measured with high accuracy can provide a basis for realistic modeling of thermo-mechanical reliability of electronic components     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

Moisture-induced failures of adhesive flip chip interconnects

Adhesive flip chip interconnect has been recognized as a promising substitute for solder interconnection due to its fine-pitch, lead-free, and low-temperature processing capabilities. As adhesives are made of polymers, moisture absorption by the polymeric resin remains as one of the principal contributors to adhesive joint failure mechanisms. In this research, the reliability performance of the adhesive flip chip in the pressure cooker test and moisture sensitivity test conditions was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different sizes of bump/pad opening in the interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between adhesive and other components in the package, which induces a hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated from the standpoint of finite element modeling. In this study, it is concluded that hygroscopic swelling assisted by loss of adhesion strength upon moisture absorption is responsible for the moisture-induced failures in these adhesive flip chip interconnects.