Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability ERA

Clear relations have been established between E-sort yield and burn-in, EFR and field failure rates for nearly 50 million high volume products in bipolar, CMOS and BICMOS technologies from different waferfabs. The correlations obey a simple model that assumes that the reliability defect density is a fraction of the waferfab defect density and that rootcauses of failures are the same. The model allows a die size independent prediction and assessment of FIT and PPM reliability levels of an IC just based on its yield, eliminating the need for excessive lifetesting. ‘Maverick’ batches are identified by more than 2 to 3 rejects per batch and can not be eliminated by scrap of low yielding wafers alone. For non-mature technologies only correlations with functional yield are found, the parametric yield loss can be disregarded. Using the results, it is shown how reliability can be improved in a fast and controlled way, even in the 1 digit FIT and PPM reliability era, by reducing waferfab defect density, elimination of special causes and implementation of screens at product test like voltage screen and Iddq testing. As the effect of yield on PPM reject level is not that strong, the latter approach can be very effective in improving reliability.     

Estimation of the reliability function using the delay-time models

The reliability model developed by Christer is used in which the notion of delay-time is involved, which is the span of time from when a defect is first detected upon inspection to when it is considered to have failed. In this paper, a new simplified formula for the reliability function is obtained, in which the delay time and the time to failure densities are exponential distributions. The MLE of the reliability function are also obtained. A numerical procedure is used to solve the results for the new model.     

基于离散模型的IC可靠性与成品率关系

集成电路的可靠性和成品率是制约半导体制造发展的两个主要因素.如何表征可靠性和成品率之间的关系是一个非常重要的问题.本文利用一种离散的成品率模型导出了二者的关系式,该关系式不仅考虑了线宽、线间距等版图的几何信息同时还考虑了与工艺有关的缺陷粒径分布等参数.通过模拟实验给出了该模型的有效性验证.     

On the Relationship of Semiconductor Yield and Reliability

Traditionally, semiconductor reliability has been estimated from the life tests or accelerated stress tests at the completion of manufacturing processes. Recent research, however, has been directed to reliability estimation during the early production stage through a relation model of yield and reliability. Because the relation model depends on the assumed density distribution of manufacturing defects, we investigate the effect of the defect density distributions on the predicted reliability, for a single-area device without repair and for a two-area device with repair, respectively. We show that for any device, reliability functions preserve an ordering of yield functions. It is also pointed out that the repair capability improves only yield but not reliability, resulting in a large value of the factor that scales from yield to reliability. In order to achieve a reliable device, therefore, we suggest to improve yield and to perform the device test such as burn-in if the scaling factor is large.     

结合版图结构信息的基本门电路故障概率估计

在门级电路可靠性估计方法中,基本门的故障概率P一般采用经验值或人为设定.本文结合基本门的版图结构信息,综合考虑了设计尺寸及缺陷特性等因素,分析了不同缺陷模型下的粒径分布数据,给出了缺陷模型粒径概率密度分布函数的参数c的计算算法,并推导出了P的计算模型.理论分析与在ISCAS85及74系列电路上的实验结果表明,缺陷的分段线性插值模型能较准确地描述电路可靠性模型的低层真实缺陷.对ISCAS85基准电路采用本文方法所得到的电路可靠度与采用美国军用标准MIL-HDBK-217方法所得到的计算结果进行了比较,验证了本文所建P模型的合理性.     

A relation model of gate oxide yield and reliability

The relationship between yield and reliability is obviously important for predicting and improving reliability during the early production stage, especially for new technologies. Previous research developed models to relate yield and reliability when reliability is defined as the probability of a device having no reliability defects. This definition of reliability is not a function of mission time and thus is not consistent with reliability estimated from the time-to-first-failure data which is commonly used. In this paper, we present a simple model to tie oxide yield to time-dependent reliability by combining the oxide time to breakdown model with a defect size distribution. We show that existing models become special cases when a single mission time is considered. As the proposed reliability function has a decreasing failure rate, the result is useful for a manufacturer seeking to find an optimal burn-in policy for burn-in temperature, burn-in voltage, and burn-in time.     

微电子工艺技术可靠性

对工艺过程进行评估的目的在于找出存在可靠性缺陷的地方，它是针对技术磨损的机理，通过对专门设计的测试结构进行封装级或圆片级可靠性测试，获取可靠性模型参数和可靠性信息，超大规模集成电路主要的三个的失效机理分别是热载流子注入效应，金属化电迁移效应和氧化层的TDDB击穿，本文对这三种失效机理分别进行了介绍，对各自对应的可靠性模型进行了说明，列举了热载流子汪入效应的寿命评价实例，说明了可靠性评价的重要性，给出了可靠性主人在工艺中的应用流程图。     

Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models

Two models for the effect of area scaling on reliability are derived from two distinct yield models with different assumptions on defect distributions. One is derived from the Poisson yield model assuming a uniform random distribution of defects as in an early model. The other is based on the negative binomial yield model to account for deviation from a uniform random distribution of defects caused by clustering. Experimental data from backend test structures show that the model based on defect clustering explains observed data well while the model assuming a uniform random distribution shows a significant departure from it.     

NRLA & MOD-Metric Models as Aids in Design Decisions

This paper reports partial results and extensions of a study at Clemson University from 1980 December to 1982 May. The purpose was to develop an integrated model set to aid in evaluating design alternatives on the availability and logistic support requirements of major weapon systems. The model set includes the Network Repair Level Analysis (NRLA) and MOD-Metric models. System design decisions concern the nominal reliability of components, the extent to which components are hierarchially designed, the accessibility of components, and whether the component will be repaired or discarded when it fails. System design includes the design of the logistic support system and its relation to the hardware. Design alternatives should be carefully investigated to determine the effects that each would have on ownership costs, performance, and availability. This model set was applied to the components of the air refueling boom of the KC-135A tanker aircraft. The 2-echelon, 2-indenture inventory system used at times by the US Air Force is assumed. In particular we report: 1) the effects of component reliability on spare stock levels and spare parts costs, and 2) the impact of component reliability on the level at which repair takes place. The models have similar data requirements and they yield useful conclusions. However, there are some difficulties. The spares decisions from MOD-Metric are not necessarily compatible with NRLA because the MOD-Metric analysis is far more sophisticated.     

Validation of yield models with CMOS/SOS test structures

A methodology assessed to implement wafer level reliability relies on the design of specific test structures which must be as similar as possible to functional circuits geometries and lay-outs. In a second step, electrical tests provide wafer level data to validate the use of the Poisson yield model which gives defect densities. It is found that chips from the central area of the wafer present randomly distributed defects whereas those from the periphery are governed by a more systematic distribution.     

一种基于改进型PCNN的织物疵点图像自适应分割方法

 针对传统脉冲耦合神经网络(Pulse Coupled Neural Network,PCNN)模型中网络参数多、不易自动选取的问题,本文在对PCNN模型进行改进的基础上,提出了一种基于改进型PCNN织物疵点图像自适应分割方法.采用了一种基于分割区域内均匀度差异最小作为最佳迭代次数判断标准,从而有效地满足了PCNN对织物疵点图像的自动分割要求.通过对不同疵点图像分割实验证明了算法对疵点分割的准确性和有效性.     

超声波探伤技术在MLCC检测中的应用研究

MLCC产品的内部微小缺陷一直是MLCC检测的难点之一,它严重影响到产品的可靠性,却又难以发现.本文对比了超声波探伤法与传统的磨片分析法对MLCC内部微缺陷的检测的结果,发现超声波探伤方法能够更精确地检测出MLCC内部的缺陷,从而分选出不良品,提高MLCC的击穿电压与高压可靠性.     

The physics of determining chip reliability

We have indicated the necessity for using statistical models to determine the reliability of deep-submicron MOSFETs. We have presented a methodology by which the reliability can be determined from short-time tests if the defect generation statistics are linked to variations in defect activation energies. We have shown that enhanced latent failures follow from our model for deep-submicron MOSFETs. Therefore, more stringent reliability standards are required, which can be validated by the use of short-time tests. Our model provides the means to calculate these novel reliability demands quantitatively     

Implications of a localised defect model for wafer level reliability measurements of thin dielectrics

In this paper a simple model of an oxide defect as a region of localised oxide thinning is used to explore the relationship between the most commonly used measurements of dielectric reliability. For each measurement it shows how the measured parameters depend on the area and effective thickness of the defect. The work shows that in constant voltage and ramped voltage stress the area and thickness of the defect may be easily separated in the measured parameters. However, in constant current and ramped current measurements all measured parameters are dependent on both area and thickness which makes the extraction of area and thickness more difficult. It is shown that, in order to be able to project from one measurement to any other, the defect area and thickness must be determined. In particular, if projections of charge to breakdown are required then the use of a model which only includes defect thinning as proposed by Lee et al, [1], is not sufficient.     

Why failure rates observe Zipf's law in operational software

The author proposes a model showing how software developers, when attempting to produce software of a given reliability level with a minimum of resources, create software whose fault content observes Phillip's and Zipf's laws. He also proposes a software reliability model based on Zipf's law that fits Adam's reliability data on nine software systems with an average correlation coefficient of 0.986. He concludes that software, when and only when optimally developed, displays operational reliability patterns conforming to Zipf's law     

TN型产品画面切换潮汐现象的分析与改善

TN型LCD产品在由L255向L0切换瞬间经常出现一种潮汐现象。该现象表现为像素边缘液晶响应延迟,有短暂的局部漏光,对品质影响较大。为改善该不良进行了研究。首先,根据不良表现出来的规律性,明确了只有摩擦弱区并不能导致不良;接着,通过大量的实测数据及电学实验分析证明了侧向电场增大到一定程度后才能使不良发生。分析表明,不良是摩擦弱区和侧向电场共同作用的结果,通过优化像素电极和数据线与摩擦弱区的位置关系,不良由2.7%下降到0.3%左右。     

巡航导弹飞控数据链信道编译码器模型及算法分析

巡航导弹飞控数据链传输的指令和数据与导弹武器紧密相关，有很高的可靠性和安全性要求。必须探寻一种高效的信道编码方法。尽可能提高编码增益。文章提出了飞控数据链信遵编码译码方案，构建了编译码器模型．并进行编译码关键算法分析和性能仿真。仿真表明，当误码率为10^-6时，可以获得7.6dB的编码增益。     

Optimal properties of the Laplace trend test for soft-reliabilitymodels

The author studies the Laplace trend test when it is used to detect software reliability growth, and proves its optimality in the frame of the most famous software reliability models. Its intuitive importance is explained, and its statistical properties are established for the five models: Goel-Okumoto, Crow, Musa-Okumoto, Littlewood-Verral, and Moranda. The Laplace test has excellent optimality properties for several models, particularly for nonhomogeneous Poisson processes (NHPPs). It is good in the Moranda model, which is not an NHPP; this justifies entirely the use of this test as a trend test. Nevertheless, the Laplace test is not completely satisfactory because neither its exact statistical-significance level, nor its power are calculable, and nothing can be said about its properties for the Littlewood-Verral method. Consequently, the author suggests that it is always better to check if it has good properties in the model, and to search for other tests whose statistical-significance level and power are calculable     

基于制造成品率模型的集成电路早期可靠性估计

缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期.     

缺陷引起的可靠性和成品率关系研究

为了在满足最低可靠性要求的同时尽量提升Ic的成品率,基于缺陷的泊松分布模型及负二项分布模型研究了由缺陷引起的Ic可靠性和成品率这两者之间的关系,并分别建立了相应的成品率一早期可靠性关系模型。基于成品率一可靠性模型,针对氧化层缺陷模型,采用模拟运算的方法,得到了随时间变化的成品率一可靠性关系模型。模型表明,在满足最低可靠性要求的同时,合理设计老化实验参数,可以最大限度地提高成品率,降低Ic制造成本。最后根据这一模型对Ic老化筛选实验的参数选择提出了优化的建议。