Multimode $G_{m}$– $C$ Channel Selection Filter for Mobile Applications in 1-V Supply Voltage

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.     

A 50–300-MHz Highly Linear and Low-Noise CMOS $Gm{hbox{-}}C$ Filter Adopting Multiple Gated Transistors for Digital TV Tuner ICs

In this paper, a highly linear and low noise CMOS active tracking low-pass filter is presented to overcome a local oscillator harmonic mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A transconductor linearization technique based on a method of multiple gated transistors is adopted to improve the linearity performance. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. Fabricated in a 0.18-$mu{hbox{m}}$ CMOS process, the filter provides a minimum input referred noise density of 5 $ {hbox{nV}}/sqrt{hbox{Hz}}$ and maximum in-band output referred third-order intercept point of 16.9 dBm, while drawing an average current of 40 mA from 1.8 V. The total chip area is 1 mm $times$ 0.9 mm.      

CMOS linear programmable transconductor suitable for adjustable Gm-C filters

A novel CMOS linear programmable transconductor is presented. It is based on a telescopic cascode operational transconductance amplifier with source degeneration implemented by means of highly linear tunable active resistors. The transconductor has been designed in a 0.5 mum CMOS technology featuring a third-order intermodulation (IM3) of -54.8 dB at 10 MHz for a 1 V_pp output voltage. Its feasibility for Gm-C filter design has been experimentally validated with a 1 MHz tunable third-order Chebyshev lowpass filter suitable for Bluetooth applications.     

A linear compact tunable transconductor for Gm-C applications

A CMOS highly linear voltage-controlled transconductor suitable for Gm-C filter design is presented. The control loop to program the transconductance maintains the input transistors in triode region with a compact topology. Measurement results for the transconductor fabricated in a 0.5-??m CMOS technology feature a spurious-free dynamic range (SFDR) of 72?dB for 1 V_pp differential inputs at 1?MHz. The voltage to current converter ensures a high linearity level for a wide transconductance range. Functionality of the transconductor is shown in a fifth-order Gm-C tunable complex filter well suited for a dual-mode Bluetooth/Zigbee transceiver.     

A Tunable Pseudo-Differential OTA With $-78~{hbox {dB}}$ THD Consuming 1.25 mW

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-mum CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-V_pp input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption.     

Low-voltage transconductor with high linearity and large bandwidth

A linear tunable CMOS transconductor is proposed which uses a new low-voltage supercascode transistor to provide a high output resistance. Using a standard 0.8 /spl mu/m CMOS technology, simulation results are provided that show the operation of the proposed transconductor with a 1.2 V peak-to-peak differential input signal and 1.5 V supply voltage. The proposed transconductor features a high linearity and more than 100 MHz bandwidth.     

A CMOS “soft-switched” transconductor and itsapplication in gain control and filters

This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today's submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are “soft-switched” by means of MOS transistors. The transconductance is continuously tunable. A transconductor, using a device in which the degeneration resistors and “soft switches” are merged, is optimized for a maximum tuning range and can be used in variable gain stages like in an automatic gain control (AGC) circuit. Besides, a third-order 5.5 MHz low-pass filter has been realized in a 0.5-μm CMOS process using the “soft-switched” transconductor. At a 3.3 V supply voltage the filter dissipates 12 mW and the dynamic range equals 62 dB where the total harmonic distortion (THD) is -48 dB for an input voltage of 1 Vpp     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

New CMOS Fully‐Differential Transconductor and Application to a Fully‐Differential Gm‐C Filter

A new CMOS voltage‐controlled fully‐differential transconductor is presented. The basic structure of the proposed transconductor is based on a four‐MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ± 1 V at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully‐differential Gm‐C low‐pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using 0.35 μm technology are also given.     

A novel pseudo differential transconductor for IEEE 802.11 WLANs

A novel pseudo differential transconductor for multi-mode analog baseband channel selection filter is presented. The highly linear transconductor is designed based on the dynamic source degeneration and predistortion cancellation technique. Meanwhile, wide tuning range is achieved with the current division technique. An LC ladder third-order Butterworth low-pass filter implemented with transconductors and capacitors was fabricated by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency ranging from 4 to 20 MHz. The tuning range is wide enough for the specifications of IEEE 802.11a/b/g/n Wireless LANs under the consideration of low power consumption and linearity requirement. The maximum power consumption is 3.61 mA at the cutoff frequency of 20 MHz.     

截止频率精确可调跨导电容滤波器实现

提出了一种新的利用开关电容技术调节偏置电流值大小的电路,应用该电路可以精确调节跨导运放Gm值的大小。采用既具有电压共模负反馈(CMFB)电路, 又同时具有工作在线性区的MOS管作源极反馈有源电阻, 实现其良好线性度的跨导运放。设计了三阶椭圆函数低通滤波器,并实现其频率的精确可调。应用台积电(TSMC)2层多晶硅,4层金属(2P4M),3.3V电源电压,0.35m CMOS工艺Spice model仿真得到的频响曲线与理想情况十分接近。     

A GaAs Junction Varactor With a Continuously Tunable Range of 9 : 1 and an of 57 dBm

In this letter, a junction varactor is presented with a large capacitance tuning range, while providing very high linearity. Such varactors are extremely useful in adaptive RF applications, which directly benefit from passive components with high tuning range and high linearity. Using a preproduction GaAs process technology and third-order intermodulation $(IM_{3})$ cancellation techniques, a very linear device is created with a capacitance tuning range as large as 9 : 1 over a control voltage range from 0 to 15 V. Its third-order output intercept point is 57 dBm; the average quality factor is $sim$50, and the breakdown voltage is 28 V. These measured results represent the current state-of-the-art in tuning range, linearity, and quality factor among all existing continuously tunable elements.      

A Novel Tunable Transconductance Amplifier Based on Voltage-Controlled Resistance by MOS Transistors

A new tunable transconductance amplifier is proposed for the programmable analog signal processing or low power filter applications. The transconductor linearization is based on the compensation of nonlinear behaviour by two MOS transistors. The transconductance amplifier in this brief exhibits the good common-mode dynamic range and the voltage-controlled transconductance. HSPICE circuit simulation using 0.18-$muhbox m$standard CMOS technology shows the$pm$50% tunable transconductance range with the$pm$0.2-V control voltage, and the linearity of less than 60 dB in the total harmonic distortion for the 0.6$hbox V_ PP$input signal.     

Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 m CMOS technology are provided, confirming on silicon the validity of the proposed approach.     

Low‐Voltage Tunable Pseudo‐Differential Transconductor with High Linearity

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage‐to‐current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of ?67 dB at 1 MHz for an input of 1 V_pp and a supply voltage of 1.8 V.     

A 40-MHz Double Differential-Pair CMOS OTA With $-{hbox{60-dB}}$ IM3

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 V_pp at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1times10^-3 mm² and the power consumption is 9.5 mW under a 1.5-V supply voltage.     

Highly linear programmable balanced current scaling technique in moderate inversion

A technique to achieve highly linear current scaling in CMOS technologies is proposed. It is based on two balanced electronically programmable current mirrors operating in moderate inversion. The scaling factor can be continuously adjusted in a wide range. This technique can be employed to achieve or to extend gain adjustment in amplifiers. As an application example, a variable-gain differential current amplifier and a tunable transconductor are presented. Measurement results of the transconductor implemented in a 0.5-/spl mu/m CMOS technology validate in silicon the proposed approach.     

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$mu$ m CMOS

Fully reconfigurable transceivers are required to answer the low-power high flexibility demand of future mobile applications. This paper presents a fully reconfigurable G_m-C biquadratic low-pass filter which offers a large range of both frequency and performance flexibility. First, a design approach is proposed focusing on linearity properties by extending Volterra analysis from circuit to architectural level in order to optimize the filters performance. Secondly, a novel switching technique is discussed that allows a bandwidth tuning over more than two orders of magnitude starting from 100 kHz up to 20 MHz and which uses only gate transistor capacitance. Fundamental to this technique is that the power consumption can be traded with the desired performance. Furthermore, the quality factor, noise level and linearity are all programmable over a very wide range. The biquad is processed in a 0.13-mum CMOS technology and operates at different supply voltages down to less than 0.8 V. For a 1.2-V supply, the filter consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) for a low noise setting around 25 to 35 muVrms integrated over the filter bandwidth achieving an third-order intermodulation intercept point of 10 dBVp.     

A New Linearized CCII-Based Fully Differential CMOS Transconductor Used for \hbox {G}_\mathrm{m}-C Active Filters Implementation

The paper presents a new linearized, of high performance, fully differential transconductor, based on class AB second generation current conveyor (CCII) in CMOS technology. The proposed circuit is composed by two positive CCII cells connected in series and a common mode feedback loop. Unlike other CMOS circuits on the basis of CCII reported in the literature, the proposed transconductor cell allows to obtain a higher transconductance value, an improved linearity and operates at high frequency for a 3.3 V supply voltage. As an application, the new transconductor cell in CMOS technology is used for designing a 4th order differential $\hbox {G}_\mathrm{m}$ -C low-pass filters in different approximations (Butterworth and Chebyshev) operating up to 300 MHz cut-off frequency. The simulations performed in 130 nm CMOS process confirm the theoretical results.     

A <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript><Emphasis Type="Italic">-C</Emphasis> continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.