Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

一种改进的高速彩票总线仲裁器

随着半导体工艺的发展,片上系统(System-on-Chip, SoC)内部集成的不同功能IP(Intellectual Property)核越来越多。各IP核通过总线方式连接,多核同时抢占总线很大地制约了片上系统的性能。高效的总线仲裁器可以解决多核抢占总线引起的冲突和竞争问题,提升片上系统性能。该文提出一种改进的高速彩票总线仲裁器。使用4相双轨协议代替时钟实现彩票抽取机制以防止彩票丢弃,采用异步流水线交叉并行的工作方式以提升工作速度。在NINP(NonIdling and NonPreemptive)模型下通过65 nm CMOS工艺的Xilinx Virtex5板级验证,相比经典彩票仲裁器和动态自适应彩票仲裁器,具有更好的带宽分配功能,有效避免撑死和饿死现象,工作速度提高49.2%以上,具有一定的功耗优势,适用于有速度要求的多核片上系统。     

基于路径遍历算法的SoC总线测试矢量集压缩

多跳变(MT)故障模型是目前提出的具有完整故障覆盖率的一种总线测试故障模型,但其测试矢量集存在严重的矢量冗余。提出了一个基于路径遍历算法的测试矢量压缩方法,以MT模型为基础,经压缩简化后得到更适用于SoC总线测试的BMTC故障模型。实验结果表明,使用提出的压缩方法,可以在保证MT模型故障覆盖率不变的情况下,将测试矢量数减少至原来的1/8,从而大大节省总线测试成本,提高测试效率。     

基于总线负载的SoC自适应时钟频率调节系统

针对当前总线频率配置存在静态预设方式性能浪费高、动态调频方式调节滞后、调节粒度粗和硬件开销过大等问题,提出了一种片上系统中基于总线负载的自适应时钟频率调节系统。通过总线时钟的选择性关断和基于总线历史负载状态的负载预测技术,有效解决了上述问题。SoC的总线功耗由36.089 mW降低到19.581 mW,下降了45.74%。     

一种基于频繁值和位变换感知的数据总线节能方法

深亚微米工艺下,片上数据总线能耗占嵌入式多核芯片能耗的比重越来越大.FV-MSB（Frequent Value-Most Significant Bits）方法降低了片外数据总线的能耗,但对于非频繁值和频繁高位值的低位部分未做处理,为进一步降低片上总线动态能耗,设计了一种基于频繁值和位变换感知的片上总线节能方法.利用频繁值和对位变换数的感知选择编码方式,大幅减少了数据总线上的位变换,有效降低了总线动态能耗.70nm工艺下,仿真实验结果显示,本文的方法最大节能比例可达17.76%,平均节能比例达16.91%,较FV-MSB方法使节能比例提高了6.28%.并且节能比例随λ的变化趋势表明本方法在未来工艺尺寸缩小时仍能发挥作用.     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

SoC interconnection protection through formal verification

The wide adoption of third-party hardware Intellectual Property (IP) cores including those from untrusted vendors have raised security concerns for system designers and end-users. Existing approaches to ensure the trustworthiness of individual IPs rarely consider the entire SoC design, especially the IP interactions through SoC bus. These methods can hardly identify malicious logic (or design flaws) distributed in multiple IPs whereas individual IPs fulfill security properties and can pass the security testing/verification. One possible solution is to treat the SoC as one IP core and try to verify security properties of the entire design. This method, however, suffers from scalability issues due to the large size of SoC designs with multiple IP cores integrated. In this paper, we present a scalable SoC bus verification framework trying to verify the security properties of SoC bus implementation where the bus protocol plays the role of the golden reference. More specifically, finite state machine (FSM) models will be constructed from the bus implementation and the trustworthiness will be verified based on the property set derived from the bus protocol and potential security threats. Along with IP level formal verification solutions, the proposed framework can help ensure the security of large-scale SoCs. Experimental results on ARM AMBA Bus demonstrate that our approach is applicable and scalable to prevent information leakage and denial-of-service (DoS) attack by verifying security properties.     

Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems

In this paper we show that the energy reductions obtained from using two techniques, data remapping (DR) and voltage/frequency scaling of off-chip bus and memory, combine to provide interesting trade offs between energy, execution time and power. Both methods aim to reduce the energy consumed by the memory subsystem. DR is a fully automatic compile time technique applicable to pointer-intensive dynamic applications. Voltage/frequency scaling of off-chip memory is a technique applied at the hardware level. When combined together, energy reductions can be as high as 49.45%. The improvements are verified in the context of three OLDEN pointer-centric benchmarks, namely Perimeter, Health and TSP.     

A dictionary-based en/decoding scheme for low-power data buses

As bus lengths on multihundred-million transistor systems-on-a-chip (SoC) grow, and as interwire capacitances of sub-0.10 /spl mu/m technologies advance, the resulting high-switching capacitances of buses (and interconnects in general) have a nonnegligible impact on the power consumption of a whole SoC. This trend has been recognized and recently addressed by various research groups. We address this problem by introducing our bus encoding technique, adaptive dictionary-encoding scheme "ADES" that minimizes the power consumption of data buses through a dictionary-based encoding technique. Based on exploration of data properties on buses, our technique saves on average more than 25% of bus energy compared to the nonencoded cases using a large set of real-world applications for both address and data buses. Furthermore, we compare our technique to the best-known data bus encoding techniques to date and we find that it exceeds all of them in terms of energy savings for the same set of applications.     

Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis

This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.     

基于3G SIM卡SoC芯片设计的AMBA总线的精简策略

AMBA总线是SoC设计中普遍采用的总线架构,它对许多具体的设计项目往往显得过于庞大,结合3G SIM卡SoC芯片的设计,研究了AMBA总线架构的若干精简策略,提出了一些对总线进行裁剪的参考方法,经过AHB VIP验证环境表明结果可行.该方法对基于AMBA架构的SoC芯片设计有着一定的参考意义.     

一种多媒体系统芯片M-SoC的总线调度策略

多媒体系统芯片(M-SoC)是一种典型的多任务系统芯片.芯片内部众多的数据请求源都要通过总线访问单一的片外存储器,合理调度这些总线请求成为系统设计的关键.本文通过详细分析总线上片内外数据通道的特点和数据流量,给出了一种基于多通道DMA的总线调度策略,并将该策略成功运用于单芯片音视频解码系统芯片的总线设计中.该策略有效地融合了DMA请求和总线总裁问题,普遍适用于片级总线多请求的多媒体系统芯片.     

一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计

Cache作为处理器和系统总线之间的桥梁,是芯片功耗的主要来源,低功耗Cache设计在嵌入式芯片设计中具有重要意义.传统Cache设计一般依赖于特定体系结构,难以在不同的系统中进行集成,通用性差.本文提出了一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计.实验结果显示,本设计可以显著降低Cache功耗和提高系统性能.     

参数化总线桥的设计及其可重用性测量

基于IP重用的设计方法是提高SoC设计效率的有效途径。为了使IP可以多次重用于不同系统体系结构和不同应用场合,应该尽可能提高IP的可配置能力,参数化设计是实现可配置的一种常用方法。文中研究了一个参数化总线桥IP软核的设计,并使用LOC作为度量指标定量地分析了参数化设计方法和非参数化设计对IP可重用性带来的影响。     

Bus-switch coding for reducing power dissipation in off-chip buses

We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycle-accurate simulation of industrial benchmarks in conjunction with post-layout evaluation of speed, power and area overhead.     

一款嵌入式芯片总线仲裁器的设计和评估

针对片上系统(SoC)总线设计中仲裁机制的选取往往局限于抽象的定性分析,以一款嵌入式处理器芯片为设计平台,实现了固定优先级、轮转优先级和混合优先级的仲裁电路设计,并建立了仿真测试平台,通过仿真对总线主设备的总线占有率、最差等待响应时间进行了定量分析比较,得出了混合优先级仲裁机制较单一的固定优先级与轮转优先级仲裁机制在体现公平性与优先性上更有效的结论,对其他嵌入式系统总线的仲裁设计与改进提供了很好的参考.     

高稳定性无片外电容低压差线性稳压器的设计

设计了一款无片外电容低压差线性稳压器(LDO),与传统的LDO相比,此LDO消除了传统结构中所需的片外电容,可更好地应用于全集成低功耗的片上系统(SoC)中。针对无片外电容LDO没有外部等效零点补偿这一特点,采用一种折叠输入推挽输出误差放大器结构,结合密勒补偿以及一阶RC串联零点补偿两种方案,有效地改善了无片外电容LDO的稳定性。电路采用SMIC0.18μm CMOS工艺实现,面积为0.11 mm2,最大负载电容100 pF,输入电压为1.8 V时,输出电压为1.5 V,静态电流31.8μA,压差为160 mV。     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

系统芯片中AMBA总线串扰故障的自测试方法

系统芯片(SoC)技术的发展使得芯片内总线长度大大增加；芯片速度按照摩尔定律成倍提高(高达GHz)，总线间的串扰(Crosstalk)现象也日益严重，因此关于串扰的故障模型和自测试技术越来越受到关注。本文利用最大侵扰故障MAF(Maximal Aggressor Fault)模型，提出了一种SoC芯片中总线串扰故障的自测试方法。利用该方法，SoC芯片中地址、数据和控制总线的串扰故障均得到了测试，实验结果也表明其硬件开销较其它方案大大降低。     

A New Multi‐site Test for System‐on‐Chip Using Multi‐site Star Test Architecture

As the system‐on‐chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.