Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors

In this paper, we present a technique called Digital Captureless Delay Testing Sensors (DCDTS). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions due to excessive resources (mainly test time or tester memory) requirements, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The DCDTS random patterns are internally generated, requiring virtually no additional test application time or tester memory. As such, DCDTS can be seen as a new way to save both test time and tester memory. Results show that DCDTS can achieve pattern volume and test time reduction factors of up to 3. When used in complement to existing compression techniques, DCDTS has the potential to triple their pattern volume (test application time) compression (reduction) rate. Area/performance overhead and technical obstacles to automation are minimal. An automated sensor selection procedure is proposed, with reasonable CPU time.     

数字电路测试向量自动生成系统的比较

把遗传算法与蚂蚁算法运用于组合电路向量自动生成系统,并比较两者性能的优劣,根据实验结果进一步提出优化组合方案,将此方案应用于同步时序电路的测试向量自动生成系统中。提出一种优化的数字电路的测试向量自动生成系统。这个系统集合了蚂蚁算法和遗传算法的优点,使系统能在更短时间生成更小的测试集,而又能达到原先的故障覆盖率。     

雷达天线测试中的若干结构问题

波瓣测试是低副瓣、超低副瓣天线研制中不可或缺的一个重要环节,结构人员积极介入其中是必要而有益的。本文就如何处理地面雷达天线远场测试中常见的若干结构问题阐述拙见,祈对测试工作和有关人员有所裨益。     

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

A new approach for structural, fault-oriented analog test generation methodology to test for the presence of manufacturing-related defects is proposed. The output of the test generator consists of optimized test stimuli, fault coverage and sampling instants that are sufficient to detect the failure modes in the circuit under test. The tests are generated and evaluated on a multistep ADC taking into account the potential fault masking effects of process spread on the faulty circuit responses. Similarly, the test generator results offer indication for the circuit partitioning within the framework of circuit performance, area and testability.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing

The selection of test cases to satisfy a structural testing criterion is a very important task because it concerns the quality of the generated test cases. The question is “How to select a test case or path to cover an element required by a structural criterion?” The Constraint Based Criteria are proposed with the goal of answering this question and improving the efficacy, that is, the number of revealed faults. These criteria permit the use of different testing strategies by associating constraints to the required elements. The constraints describe faults generally not revealed by the structural technique. The Constraint Based Criteria can also be used to assess test data sets adequacy.     

电子产品的(雷击)浪涌防护标准及测试

本文首先就电子产品的雷击浪涌损害机体及防护方式进行了简要的说明.接着通过对几个常用的电子产品浪涌检测标准的讨论就电子产品雷击浪涌防护测试项目选择,测试方法、判断准则等方面进行了重点介绍,以方便大家在电子产品的浪涌防护设计和测试标准有一个全面的把握.     

Test chip based approach to automated diagnosis of CMOS yieldproblems

The authors describe a design approach for, and experimental results obtained from, a test chip developed for the purpose of automated diagnosis of random-defect-dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Test structure selection, sizing, layout, testing, and data analysis are discussed, and examples of rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnosis are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are summarized     

HDTV图像清晰度复合测试图

本文设计、生成了HDTV图像清晰度复合测试图。按在极坐标系建立的数学模型，由计算机逐象素编程计算、生成的该测试图，精度高，便于修改，已在定量测定数字图像清晰度中得到应用。     

An Error Rate Based Test Methodology to Support Error-Tolerance

Error-tolerance is an innovative technique to address the problem of low yields in nanometer very large scale integrated (VLSI) circuitry, which is the backbone of the system-on-a-chip (SOC) revolution. The basic principle of error-tolerance is that some chips may occasionally produce erroneous outputs, but still provide acceptable performance when used in certain systems. Using these chips in such systems results in an increase in effective yield. In this paper, a fault-oriented test methodology is presented for classifying whether or not a chip is acceptable based on error rate estimation. A sampling method is proposed to estimate error rate associated with each possible fault in the target circuit. According to this information, an approach is developed to identify a list of faults that are acceptable with respect to a specified upper bound on expected error rates of acceptable chips. Furthermore, a test pattern selection method, and an output masking technique are presented to identify tests which detect all of the unacceptable faults, and as few acceptable faults as possible, so as to maximize the effective yield. Experimental results indicate the high effectiveness of the proposed error rate estimation method, and the degree to which yield can be enhanced.     

试验天线对雷达罩传输效率的影响及分析

在雷达罩电性能测试过程中,需要用到试验天线,试验天线的类型、极化方式和口径尺寸对雷达罩电性能测试结果有一定影响。文中对试验天线口径尺寸对雷达罩传输效率的影响程度进行了仿真计算,通过对比测试验证了仿真计算的正确性。计算和测试结果表明:当试验天线与装机天线口径尺寸差别不大时,试验天线口径尺寸对传输效率的影响较小。在工程实践中,当无法得到装机天线时,可以用类型相同、极化方式相同、口径相近的天线作为试验天线,以完成传输效率的测试。     

耗材优化工艺试验研究

通过调研分析选取了三类耗材选型方案来进行工艺试验研究,主要包括焊膏、清洗剂和助焊剂,并且依托于典型的印制板以及元器件来完成试验件。基于方案中的耗材基础性能测试、印制板组件试验件焊点机械强度测试以及焊点微组织结构分析来完善耗材选型,优化匹配性设计,确定最终耗材型号,进一步提高焊点质量和可靠性。     

16位单片机测试技术研究

集成电路测试是保证产品质量的重要手段，如何检测MCU类复杂大规模集成电路是测试的难点。文章以实际测试过的电路80C196KC为例，详细地介绍了“硬件学习法”生成测试码点的硬件构成和测试向量的采集方法。为实现对80C196KC丰富指令及各种寻址方式的完全测试，给出了测试指令的序列结构和数据结构。在此基础上给出了生成测试向量、测试A／D转换器及直流、交流参数的测试方法.     

基于虚拟仪器技术的雷达测试系统研究

介绍了基于GPIB虚拟仪器技术的雷达自动测试系统的硬件构成和软件设计方法。通过对虚拟仪器技术的深入研究,重点论述了虚拟仪器技术的特点及其对本系统的有力支持,同时对雷达和方向图、差方向图、雷达轴比以及增益等雷达分系统性能测试方法也进行了详细的论述,并通过几个典型的软件设计模型分析了影响测试结果可靠性的诸多因素和环节。     

A High-Speed Pseudorandom Test Pattern Generator

Real-time built-in self-testing (BIST) of digital devices that incorporate functional modules of various speed is considered. A method of designing a pattern generator is suggested. This generator is capable of forming pseudorandom test patterns both with the normal speed (one test vector per clock cycle) and with a speed several times higher (several test vectors per clock cycle). With these generators, at-speed testing of multichip module components can be performed to detect both stuck-at and ac faults.     

集成电路极性测试“微整机”研究与应用

集成电路极性测试一般指选择电路一个特定管脚进行电性能量测,快速判断电路放置是否反向、错位等,实现原理和集成电路开短路测试原理一致。目前集成电路极性测试多数依赖于功能强大、应用成熟的集成电路自动测试机(Automatic Test Equipment,ATE)实现,但是测试性价比没有任何竞争力。基于集成电路极性测试原理,采用纯硬件制作一款集成电路极性测试"微整机",在极性测试上达到与ATE同样的测试能力,并能和机械手(Handler)进行信息交互,实现自动化测试,具备简单、稳定、高效和极低成本的特点。     

一种基于大动态微波功率测量的雷达天线方向图测试方法

本文提供了一种雷达天线方向图新的测试方法,利用大动态范围的微波小功率计,最低可测量出微瓦级的功率信号,直接测量雷达天线各个方位接收到的功率信号,解决了传统的雷达天线方向图测试方法步骤繁多、测量误差大、动态范围小等不足,适用于具有良好电子对抗要求的新型低副瓣或极低副瓣雷达天线的方向图测试,完全满足工程测试的需要。     

New Techniques for Deterministic Test Pattern Generation

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time.     

隔行扫描电视系统"并行"现象测试图

根据隔行扫描的原理,提出了一种定量测定隔行扫描电视系统隔行扫描性能的原理和方法,设计了相应测试信号,能直观地测定并行方向和程度。