A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining

We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.Shih-Hao Wang was born in Tainan, Taiwan, R.O.C. in 1977. He received the M.S. degree in Electrical and Control Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001, where he is currently working toward the Ph.D. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Wen-Hsiao Peng was born in Hsin-Chu, Taiwan, Republic of China, in 1975. He received the B.S. and the M.S. degrees in Electrics Engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, in 1997 and 1999respectively. During 2000–2001, he was an intern in Intel Microprocessor Research Lab, U.S.A. In 2002, he joined the Institute of Electronics of National Chiao-Tung University, where he is currently a Ph.D candidate. His major research interests include scalable video coding, video codec optimization and platform based architecture design for video compression applications. Since 2000, he has been working with video coding development and implementation. He has actively contributed to the development of MPEG-4 Fine Granularity Scalability (FGS) and MPEG-21 Scalable Video Coding (Now, MPEG-4 Part 10 AVC Amd.1).Yu-Wen Hereceived his Ph.D. degree in computer application from Tsinghua University in 2002. He was a lecture of the Department of Computer Science and Technology from 2002 to 2003 in Tsinghua University. In 2004, he joined Internet Media group of Microsoft Research Asia.His research interests include video coding, transmission and embedded multimedia application systems.Guan-yi Lin was born in Kaohsiung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and communication systems design.Cheng-Yi Lin was born in Tainan, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are on-chip communication and testing.Shih-Chien Chang was born in Taichung, Taiwan in 1981. He received the B.S. degree in Electronics Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2003, where he is currently working toward the M.S. degree in the Institute of Electronics.His research interests are video compression and VLSI implementation.Chung-Neng Wang was born in PingTung, Taiwan, in 1972. He received the B.S. degree and Ph.D degree in computer science and information engineering from National Chiao-Tung University (NCTU), HsinChu, Taiwan in 1994 and 2003, respectively. He joined the faculty at National Chiao-Tung University in Taiwan, R.O.C in January 2003.Since 2001 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process. He has made more than 18 contributions to the MPEG committee over the past 4 years. He published over 23 technical journal and conference papers in the field of video and signal processing. His current research interests are video/image compression, motion estimation, video transcoding, and streaming.Tihao Chiangwas born in Cha-Yi, Taiwan, Republic of China, 1965. He received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1987, and the M.S. degree in electrical engineering from Columbia University in 1991. He received his Ph.D. degree in electrical engineering from Columbia University in 1995. In 1995, he joined David Sarnoff Research Center as a Member of Technical Staff. Later, he was promoted as a technology leader and a program manager at Sarnoff. While at Sarnoff, he led a team of researchers and developed an optimized MPEG-2 software encoder. For his work in the encoder and MPEG-4 areas, he received two Sarnoff achievement awards and three Sarnoff team awards.Since 1992 he has actively participated in ISO’s Moving Picture Experts Group (MPEG) digital video coding standardization process with particular focus on the scalability/compatibility issue. He is currently the co-editor of the part 7 on the MPEG-4 committee. He has made more than 90 contributions to the MPEG committee over the past 10 years. His main research interests are compatible/scalable video compression, stereoscopic video coding, and motion estimation. In September 1999, he joined the faculty at National Chiao-Tung University in Taiwan, R.O.C. Dr. Chiang is currently a senior member of IEEE and holder of 13 US patents and 30 European and worldwide patents. He was a co-recipient of the 2001 best paper award from the IEEE Transactions on Circuits and Systems for Video Technology. He published over 50 technical journal and conference papers in the field of video and signal processing.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Scheduling for time-division based shared channel allocation for UMTS

The Universal Mobile Telecommunications System (UMTS) adopts the WCDMA technology as the radio access interface to provide variable transmission rate services. There are four classes of connections identified in UMTS, which are the conversational, streaming, interactive, and background connections. To efficiently utilize radio bandwidth, the shared channel approach is proposed to deliver the packets for the interactive and background connections. This paper proposes a “Shared-Channel Assignment and Scheduling” (SCAS) algorithm to periodically allocate shared channels to serve interactive and background connections. We conduct formal mathematical proofs and simulation experiments to investigate the performance of the SCAS algorithm. We formally prove that with SCAS, a shared channel can be fully utilized (i.e., the utilization of a shared channel can be up to 100%) to serve the interactive connections. Our analysis indicates that compared with the previously proposed shared channel allocation and scheduling algorithms, there are less computation and communication overheads introduced in the SCAS algorithm. The results of the simulation experiments indicate that it is preferred to set up the Transmission Time Interval (TTI; that is, the unit of time interval for shared channel allocation) smaller to optimize the performance of the SCAS algorithm, including the shared channel utilization and the average waiting time of a connection before getting transmission service. A preliminary version [11] of this work has been accepted by IEEE Wireless Communications and Networking Conference 2004. This paper is an extension of the proposed algorithm, and simulation and analysis are conducted to investigate the performance of the proposed algorithm. Chai-Hien Gan was born in Malaysia in 1971. He received his BS degree in computer science from Tamkang University in 1994, Taipei County, Taiwan, and both his MS. and Ph.D. degrees in computer science and information engineering from National Taiwan University, Taipei, Taiwan, in 1996 and 2005, respectively. Since March 2005, he has been a Research Assistant Professor in Department of Computer Science, National Chiao Tung University, R.O.C. His current research interests include wireless mesh networks, mobile computing, personal communications services, and wireless Internet. Phone Lin received his BSCSIE degree and Ph.D. degree from National Chiao Tung University, Taiwan, R.O.C. in 1996 and 2001, respectively. From August 2001 to July 2004, he was an Assistant Professor in Department of CSIE and Graduate Institute of Graduate of Networking and Multimedia, National Taiwan University, R.O.C. Since August 2004, he has been an Associate Professor in Department of CSIE and Graduate Institute Graduate of Networking and Multimedia, National Taiwan University, R.O.C. His current research interests include personal communications services, wireless Internet, and performance modeling. Dr. Lin is an Associate Editor for IEEE Transactions on Vehicular Technology, Editor for IEEE Wireless Communications special issue on Mobility and Resource Management and a Guest Editor for ACM/Springer MONET special issue on Wireless Broad Access. He is also an Associate Editorial Member for the WCMC Journal. P. Lin’s email and website addresses are plin@csie.ntu.edu.tw and http://www.csie.ntu.edu.tw/~plin, respectively. Nei-Chiung Perng is presently a Ph.D. student in the Department of Computer Science and Information Engineering, National Taiwan University. He received his Bachelor and Master degrees in the Department of Computer and Information Science, National Chiao Tung University in 1999 and 2001, respectively. His research interests include real-time systems and scheduling algorithms. Tei-Wei Kuo received B.S.E. degree in computer science and information engineering from National Taiwan University in Taipei, Taiwan, in 1986. He received the M.S. and Ph.D. degrees in computer sciences from the University of Texas at Austin in 1990 and 1994, respectively. He is currently a Professor and the Chairman of the Department of Computer Science and Information Engineering of the National Taiwan University, Taiwan, ROC. He was an Associate Professor in the Department of Computer Science and Information Engineering of the National Chung Cheng University, Taiwan, ROC, from August 1994 to July 2000. Dr. Kuo is a senior member of the IEEE computer society. His research interest includes embedded systems, real-time process scheduling, real-time operating systems, and real-time databases. He has over 100 technical papers published or been accepted in international journals and conferences and has a book “Real-Time Database Systems: Architecture and Techniques” published by Kluwer Academic Publishers (ISBN 0-7923-7218-2, USA). He is the Program Co-Chair of IEEE 7th Real-Time Technology and Applications Symposium, 2001, and an associate editor of the Journal of Real-Time Systems since 1998. He is an executive committee member of the IEEE Technical Committee on Real-Time Systems in 2005 and the steering committee chair of IEEE RTCSA’05. Dr. Kuo has consulted for government and industry on problems in various real-time and embedded systems designs. Dr. Kuo received several research awards in Taiwan, including the Distinguished Research Award from the ROC National Science Council in 2003 and the Young Scholar Research Award from Academia Sinica, Taiwan, ROC, in 2001. Ching-Chi Hsu was born in Taipei, Taiwan in 1949. He received his BS degree in physics from National Tsing Hwa. University in 1971, Hsishu, Taiwan, and both his MS. and Ph.D. degrees in computer engineering from EE department of National Taiwan University, Taipei, Taiwan, in 1975 and 1982, respectively. In 1977, he joined the faculty of the Department of Computer Science and Information Engineering at National Taiwan University and became an associate professor in 1982. During the years between 1987 and 2002, he was first engaged as a professor and became the chairman of the department. During his tenure in National Taiwan University, Dr. Hsu was a visiting scholar of Computer Science Department, Stanford University from 1984 to 1985. After serving in National Taiwan University for over 25 years, Dr. Hsu had left and was promoted as the president of Kai Nan University in 2002. Starting from February 2004, Dr. Hsu has been the executive vice president of the Institute for Information Industry in which he is mainly in charge of accelerating the growth of information industry in the whole nation. His research interests include distributed processing of data and knowledge, mobile computing and wireless networks.     

Repacking on Demand for Hierarchical Cellular Networks

In mobile telecommunications operation, radio channels are scarce resources and should be carefully assigned. One possibility is to deploy the hierarchical cellular network (HCN). This paper studies a HCN channel assignment scheme called repacking on demand (RoD). RoD was originally proposed for wireless local loop networks. We expend this work to accommodate mobile HCN. A simulation model is proposed to study the performance of HCN with RoD and some previously proposed schemes. Our study quantitatively indicates that RoD may significantly outperform the previous proposed schemes. Hsien-Ming Tsai was born in Tainan, Taiwan, R.O.C., in 1973. He received the double B.S. degrees in Computer Science & Information Engineering (CSIE) and Communication Engineering, the M.S. degree in CSIE, and the Ph.D. degree in CSIE from National Chiao-Tung University (NCTU), Taiwan, in 1996, 1997, and 2002, respectively. He is currently a research specialist in Quanta Research Institute, Quanta Computer Inc. His research interests are in the areas of cellular protocols (UMTS/GPRS/GSM/DECT), cellular multimedia (MPEG-4 Audio/Speech), and embedded systems. He is an IEEE member. Ai-Chun Pang was born in Hsinchu, Taiwan, R.O.C., in 1973. She received the B.S., M.S. and Ph.D. degrees in Computer Science and Information Engineering from National Chiao Tung University (NCTU) in 1996, 1998 and 2002, respectively. She joined the Department of Computer Science and Information Engineering, National Taiwan University (NTU), Taipei, Taiwan, as an Assistant Professor in 2002. Her research interests include design and analysis of personal communications services network, mobile computing, voice over IP and performance modeling. Yung-Chun Lin was born in Kaohsiung, Taiwan, R.O.C., in 1978. He received the B.S. and M.S. degrees in Computer Science and Information Engineering (CSIE) from National Chiao-Tung University (NCTU), Taiwan, in 2001, 2003, respectively. He is currently pursuing the Ph.D. degree in CSIE. His research interests include design and analysis of a personal communications services network, the cellular protocols (UMTS/GPRS/GSM), and mobile computing. Yi-Bing Lin received his BSEE degree from National Cheng Kung University in 1983, and his Ph.D. degree in Computer Science from the University of Washington in 1990. From 1990 to 1995, he was with the Applied Research Area at Bell Communications Research (Bellcore), Morristown, NJ. In 1995, he was appointed as a professor of Department of Computer Science and Information Engineering (CSIE), National Chiao Tung University (NCTU). In 1996, he was appointed as Deputy Director of Microelectronics and Information Systems Research Center, NCTU. During 1997-1999, he was elected as Chairman of CSIE, NCTU. His current research interests include design and analysis of personal communications services network, mobile computing, distributed simulation, and performance modeling. Dr. Lin has published over 150 journal articles and more than 200 conference papers. Lin is an Adjunct Research Fellow of Academia Sinica, and is Chair Professor of Providence University. Lin serves as consultant of many telecommunications companies including FarEasTone and Chung Hwa Telecom. Lin is an IEEE Fellow and an ACM Fellow.     

Comparison of Downlink Power Allocation Mechanisms in Soft Handoff for the WCDMA System with Heterogeneous Cell Structures

Handoff in heterogeneous cellular networks is one of the hot topics for wireless networks beyond the third generation. We observe that a power exhausting issue may occur in a code division multiple access (CDMA) system with mixed-sized cells. During soft handoff in the downlink transmission, a number of base stations transmit signals to a user simultaneously. Usually, a microcell has a more stringent limitation on the total available power than a macrocell. Thus, ignoring the impact of various cell sizes, the traditional downlink power allocation techniques for soft handoff may easily consume excessive power to serve soft handoff users, while leaving insufficient power for serving other regular users.To resolve such an power exhausting issue in CDMA systems, we investigate different downlink power allocation techniques used in soft handoff subject to the impact of mixed-sized cells. For the single-site power allocation technique we consider the site selection diversity transmission (SSDT) technique, while for the multi-site power allocation we study the link proportional power allocation (LPPA), the quality balancing power allocation (QBPA), and the equal power allocation (EPA) techniques. We find that the multi-site LPPA technique can more efficiently allocate power to both handoff and non-handoff users than others. In an example with the ratio of the micrcocell radius/macrocell radius equal to 1/3, it is demonstrated that LPPA can improve the capacity over EPA, QBPA, and SSDT by 125, 30, and 5%, respectively. By taking account of measurement errors in the same case, the capacity improvements of LPPA over EPA, QBPA, and SSDT become 180, 41, and 23%, respectively.This work was supported jointly by the Lee and MTI Center for networking research, and the National Science Council, Taiwan under the contracts 90-2213-E-009-068 91-2219-E-009-016, and EX-91-E-FA06-4-4. Part of results in this paper were presented at the IEEE Globecom, Nov. 2002, and the Sixth ACM International Workshop on Modelling, Analysis and Simulation of Wireless and Mobile Systems, (MSWiM’03), Sep. 2003.Ching-Yu Liao received the B.S. and M.S. degrees in electrical engineering from Huafan Institute of Technology and National Central University (NCU), Taiwan, in 1995 and 1997, respectively. She is currently working toward the Ph.D degree in communication engineering at National Chiao Tung University (NCTU), Hsinchu, Taiwan. Also, she joins the program of Graduate Student Study Abroad (GSSA), which is sponsored by National Science Council, Taiwan, R.O.C., being a visiting graduate student in Dept. of Electrical Engineering at University of British Columbia, Vancouver, Canada, in 2004. Her research interests include handoff techniques, radio resource management, heterogeneous cellular networks, etc.Li-Chun Wang received the B.S. degree from National Chiao Tung University, Taiwan, in 1986, the M.S. degree from National Taiwan University in 1988, and the Ms. Sci. and Ph. D. degrees in electrical engineering from the Georgia Institute of Technology, Atlanta, in 1995, and 1996, respectively. From 1990 to 1992, he was with the Telecommunications Laboratories of the Ministry of Transportations and Communications in Taiwan (currently the Telecom Labs of Chunghwa Telecom Co.). In 1995, he was affiliated with Bell Northern Research of Northern Telecom, Inc., Richardson, TX. From 1996 to 2000, he was with AT&T Laboratories, New Jersey, USA, where he was a Senior Technical Staff Member in the Wireless Communications Research Department. Since August 2000, he has been an Associate Professor in the Department of Communication Engineering of National Chiao Tung University in Taiwan. His current research interests are in the areas of cellular architectures, radio network resource management, and cross-layer optimization for high speed wireless networks. Dr. Wang was a co-recipient of the Jack Neubauer Memorial Award in 1997 recognizing the best systems paper published in the IEEE Transactions on Vehicular Technology. He is holding three US patents and one more pending. Currently, he is the associate editor of the IEEE Transactions on Wireless Communications.Chung-Ju Chang was born in Taiwan, R.O.C., in August 1950. He received the B.E. and M.E. degrees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1972 and 1976, respectively, and the Ph.D degree in electrical engineering from National Taiwan University (NTU), Taiwan, in 1985. From 1976 to 1988, he was with Telecommunication Laboratories, Directorate General of Telecommunications, Ministry of Communications, Taiwan, as a Design Engineer, Supervisor, Project Manager, and then Division Director. There, he was involved in designing digital switching system, RAX trunk tester, ISDN user-network interface, and ISDN service and technology trials in Science-Based Industrial Park. In the meantime, he also acted as a Science and Technical Advisor for the Minister of the Ministry of Communications from 1987 to 1989. In 1988, he joined the Faculty of the Department of Communication Engineering and Center for Telecommunications Research, College of Electrical Engineering and Computer Science, National Chiao Tung University, as an Associate Professor. He has been a Professor since 1993. He was Director of the Institute of Communication Engineering from August 1993 to July 1995 and Chairman of Department of Communication Engineering from August 1999 to July 2001. Now, he is the Dean of the Research and Development Office in NCTU. He was an Advisor for the Ministry of Education to promote the education of communication science and technologies for colleges and universities in Taiwan since 1995. He is also acting as a Committee Member of the Telecommunication Deliberate Body. His research interests include performance evaluation, wireless communication networks, and broadband networks. Dr. Chang is a member of the Chinese Institute of Engineers (CIE).E-mail:cjchang@cc.nctu.edu.tw     

Implementation and performance evaluation for a ubiquitous and unified multimedia messaging platform

As networking technology advances, more advanced message services are provided. Users may have one or more different message accounts and devices. Before sending messages, the sender must make sure which message service the receipt currently uses. Any misjudgement may delay the time when the messages are received. To make users be able to receive messages anytime and anywhere with any kind of devices, we propose a Ubiquitous and Unified Multimedia Messaging (UMM) platform. The UMM platform integrates different message services and provides a more efficient way for message delivery. Our design does not modify the existing protocols of message services and need not involve the network operators. An analytical model is proposed to evaluate the performance of the implemented platform. Our study shows that with a large number of message services the user subscribes and long message processing time in the network, the delayed message probability can be limited within 1.5%. This performance is considered satisfactory. This paper is an extension of the work that has won the second place of the Mobile Hero contest sponsored by Industrial Development Bureau of Ministry of Economic Affairs, Taiwan, R.O.C., and was awarded USD 15,000. Phone Lin (M’02-SM’06) received his BSCSIE degree and Ph.D. degree from National Chiao Tung University, Taiwan, R.O.C. in 1996 and 2001, respectively. From August 2001 to July 2004, he was an Assistant Professor in Department of Computer Science and Information Engineering (CSIE), National Taiwan University, R.O.C. Since August 2004, he has been an Associate Professor in Department of CSIE and in Graduate Institute of Networking and Multimedia, National Taiwan University, R.O.C. His current research interests include personal communications services, wireless Internet, and performance modeling. Dr. Lin is an Associate Editor for IEEE Transactions on Vehicular Technology, a Guest Editor for IEEE Wireless Communications special issue on Mobility and Resource Management, and a Guest Editor for ACM/Springer MONET special issue on Wireless Broad Access. He is also an Associate Editorial Member for the WCMC Journal. Dr. Lin has received many research awards. He was a recipient of Research Award for Young Researchers from Pan Wen-Yuan Foundation in Taiwan in 2004, a recipient of K. T. Li Young Researcher Award honored by ACM Taipei Chapter in 2004, a recipient of Wu Ta You Memorial Award of National Science Council (NSC) in Taiwan in 2005, a recipient of Fu Suu-Nien Award of NTU in 2005 for his research achievements. Dr. Lin is listed in WHO’S WHO IN SCIENCE AND ENGINEERING(R) in 2006. Dr. Lin is a Senior Member, IEEE. P. Lin’s email and website addresses are plin@csie.ntu.edu.tw and respectively. Shan-Hung Wu received the B.S. degree from Department of Information Management, National Central University, Jhongli, Taiwan, and M.S. degree from Department of Computer Science and Information, National Taiwan University, Taipei, Taiwan. He is currently a Ph.D. candidate at Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. His research interests include distributed data management, pervasive computing, wireless and sensor networks, and performance modeling. Chung-Min Chen is Director of Telcordia Applied Research Center in Taiwan. His research interests span across areas in distributed computing, data engineering, telecommunication and network management. He received a Ph.D. in Computer Science from the University of Maryland, College Park and a B.S. in Computer Science and Information Engineering from National Taiwan University. Ching-Feng Liang received M.S. degree in electronic engineering from National Taiwan University of Science & Technology (NTUST) in 1993 and joined the Information & Communication Laboratory (ICL) of Industrial Technology Research Institute (ITRI) as an engineer. Liang has led more than 10 projects of Taiwan Ministry of Economic Affairs (MoEA) to study and develop the technologies of mobile network and services including GPRS/3G core network, WLAN/Cellular interworking and number portability service. Liang received the ITRI Award in 2005 and the Outstanding Project Award of Taiwan MoEA in 2003. Liang is currently the manager of the Core Network Department of ICL/ITRI.     

Distributed Rate Assignment for Multicarrier Multi-Cell Networks

A distributed rate assignment is proposed for the multicarrier multi-cell networks. It assigns the data rate for each subchannel in a distributed manner and needs not measure the channel gains. We show that the aggregate rate can be increased by increasing the number of iterations in this assignment. Jui Teng Wang received the B.S., M.S. and Ph.D. degrees from National Chiao Tung University, Hsinchu, Taiwan, all in communication engineering. He is now an associate professor with the Graduate Institute of Communication Engineering, National Chi Nan University, Puli, Nantou, Taiwan. His research interests are in wireless communications, communication networks and communication protocols.     

A Scalable and Reliable Multicast Routing Protocol for Ad-hoc Wireless Networks

Multicasting is an essential service for ad-hoc wireless networks. In a multicasting environment with multiple senders, receivers or meeting members, traditional multicast routing protocols must pay great overhead for multiple multicast sessions. This work presents a scalable and reliable multicasting protocol for ad-hoc wireless networks. A virtual backbone is used as a shared structure for multiple sessions. A clustering scheme is used to reduce the routing path length. A novel scheme is developed to effectively multicast packets using forwarding gates. Furthermore, a lost packet recovery scheme is developed for reliable packet transmission. This scheme can be used to improve the reliability of traditional non-acknowledged multicasting approach. Experiments were conducted to evaluate the proposed multicasting scheme and the results demonstrate that our scheme outperforms other schemes in terms of packet delivery ratio, packet delivery time, control overhead, multicast efficiency, and cost effect. Furthermore, our approach is stable for networks with high mobility and the lost packet recovery scheme is cost-effective. Chyi-Ren Dow was born in 1962. He received the B.S. and M.S. degrees in information engineering from National Chiao Tung University, Taiwan, in 1984 and 1988, respectively, and the M.S. and Ph.D. degrees in computer science from the University of Pittsburgh, USA, in 1992 and 1994, respectively. Currently, he is a Professor in the Department of Information Engineering, Feng Chia University, Taiwan. His research interests include mobile computing, ad-hoc wireless networks, agent techniques, fault tolerance, and learning technology. Jyh-Horng Lin was born in 1975. He received the B.S. and M.S. degrees in information engineering from Feng Chia University, Taiwan, in 1998 and 2000, respectively. He is currently a candidate for the Ph.D. degree in the Department of Information Engineering, Feng Chia University, Taichung, Taiwan. His research interests include mobile computing and ad-hoc wireless networks. Kun-Tai Chen was born in 1978. He received the B.S. and M.S. degrees in information engineering from Feng Chia University, Taiwan, in 2000 and 2002, respectively. He is currently an engineer in the VIA technologies, Inc. Hsinchu branch, Taiwan. His research interests include mobile computing, ad-hoc wireless networks and video decoding. Sheng-Chang Chen was born in 1979. He received his B.S. degree and M.S. degree in information engineering from Feng Chia University, Taiwan, in 2001 and 2002. He is currently a Ph.D. degree in information engineering from Feng Chia University, Taiwan. His research interests include mobile computing, ad-hoc wireless network and fault tolerance technique. Shiow-Fen Hwang was born in 1963. She received her B.S., M.S. and Ph.D. degrees in Applied Mathematics from National Chiao Tung University, Taiwan, in 1985, 1987 and 1991, respectively. Currently, she is an Associate Professor in the Department of Information Engineering, Feng Chia University, Taiwan. Her research interests include interconnection networks, mobile computing, and computer algorithms.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hard-ware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, in June 2000 and December 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Ching-Yeh Chen was born in Taipei, Taiwan, in 1980. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, in 2002. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His research interests include intelligent video signal processing, global/local motion estimation, scalable video coding, and associated VLSI architectures. Chen-Han Tsai received the B.S. degree in electrical engineering from National Taiwan University in 2002. Now he is working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include face detection and recognition, motion estimation, H.264/AVC video coding, digital TV systems, and related VLSI architectures. Chun-Fu Shen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University in 1996 and 1998, respectively. After two years of military service, he joined VIVOTEK, Inc., Taipei County, Taiwan, in 2000. He developed many video coding systems and IP camera products on DSP platforms and ASICs. His major research interests include JPEG, H.263, MPEG-4, and H.264/AVC coding systems, network camera SOC, and embedded systems. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an instructor (1981–1986), and an associate professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an associate professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a visiting consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is a professor of National Taiwan University. From 2004, he is also the executive vice president and the general director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tau Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He was also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He has served as the associate editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, the associate editor of IEEE Transactions on VLSI Systems since 1999, the associate editor of Journal of Circuits, Systems, and Signal Processing since 1999, and the guest editor of Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology since 2001. Now he is also the associate editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing and the associate editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Awards from ROC Computer Society in 1990 and 1994. From 1991 to 2005, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Outstanding Research Award from National Science Council (NSC) and the Dragon Excellence Award from Acer. He was elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

On Striping Traffic over Multiple IEEE 802.11(b) Wireless Channels

Due to interference, path loss, multipath fading, background noise, and many other factors, wireless communication normally cannot provide a wireless link with both a high data rate and a long transmission range. To address this problem, striping network traffic in parallel over multiple lower-data-rate but longer-transmission-range wireless channels may be used. In this paper, we propose a new striping method and evaluate its performances over multiple IEEE 802.11(b) channels under various conditions. Our extensive simulation results show that this method is quite effective for such an application. S.Y. Wang is an Associate Professor of the Department of Computer Science and Information Engineering at National Chiao Tung University, Taiwan. He received his Master and Ph.D. degree in computer science from Harvard University in 1997 and 1999, respectively. His research interests include wireless networks, Internet technologies, network simulations, and operating systems. He is the author of the NCTUns 2.0 network simulator and emulator, which is being widely used by network and communication researchers. More information about the tool is available at http://NSL.csie.nctu.edu.tw/nctuns.html. C.H. Hwang received his master degree in computer science from NCTU in 2002 and currently is working for a network company. C.L. Chou currently is a third-year Ph.D. student at the Department of Computer Science and Information Engineering, National Chiao TungUniversity (NCTU), Taiwan. He received his master degree in computer science from NCTU in 2002.     

Theoretical Analysis and Performance of NC-PRMA Protocol for Multichannel Wireless Networks

In this paper, we analyze the effect of duplexing schemes on the throughput and the average packet dropping probability of a new multichannel wireless access protocol which allows for non-collision packet reservation multiple access with multiple channel (NC-PRMA/MC). N _C equal-capacity, orthogonal, traffic channels are shared by M mobile users on the uplink. Transmission attempts on the uplink are made by using time-frequency signaling in every frame, which enables transmission attempts of mobile users to be conveyed to the base station without collisions. Two kinds of duplexing schemes, frequency division duplexing and shared time division duplexing, are considered in the performance analysis. Using a discrete-time Markov chain analysis, we derive the analytic expressions for the average per channel throughput and the average packet dropping probability. Computer simulation results verify the analysis. Analytical evaluation and computer simulation show that NC-PRMA/MC with shared time division duplexing improves the channel capacity, which approaches the theoretical upper bound. Jenn-Kaie Lain born in Taiwan, R.O.C., in 1973. He received the B.E. degree in engineering science from the National Cheng Kung University, Tainan, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from the National Chung Cheng University, Chiayi, R.O.C., in 1995 and 2001, respectively. Since August 2001, he joined the faculty of Department of Computer Science and Information Engineering at Shu-Te University, Kaohsiung, Taiwan, R.O.C., as an Assistant Professor. He has been on the Faculty at National Yunlin University of Science and Technology, Yunlin, Taiwan, R.O.C., since August 2002 and currently holds the position of Assistant Professor in the Institute of Electronic and Information Engineering. His current research interest is in the field of coding and modulation as well as efficient receiver designs for broadband wireless communications. Jyh-HorngWen received his B.S. degree in Electronic Engineering from the National Chiao Tung University, Hsing-Chu, Taiwan, in 1979 and the Ph.D. degree in Electrical Engineering from the National Taiwan University, Taipei, in 1990. From 1981 to 1983, he was a Research Assistant with the Telecommunication Laboratory, Ministry of Transportation and Communications, Chung-Li, Taiwan. From 1983 to 1991, he was a Research Assistant with the Institute of Nuclear Energy Research, Taoyun, Taiwan. Since February 1991, he has been with the Institute of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, first as an Associate Professor and, since 2000, as a Professor. He was also the Managing Director of the Center for Telecommunication Research, National Chung Cheng University, from Aug. 2000 to July 2004. Currently, he is also the Dean of General Affairs, National Chi Nan University. He is an Associate Editor of the Journal of the Chinese Grey System Association. His current research interests include computer communication networks, cellular mobile communications, personal communications, spread-spectrum techniques, wireless broadband systems, and gray theory. Prof.Wen is a member of the IEEE Communication Society, the IEEE Vehicular Technology Society, the International Association of Science and Technology for Development,the Chinese Grey System Association, and the Chinese Institute of Electrical Engineering.     

BER Performance of Wireless BPSK Communication System in Tunnels With and Without Traffic

The bit error rate (BER) performance for high-speed personal communication service in tunnels with and without traffic is investigated. The impulse responses of tunnels for any transmitter–receiver location are computed by shooting and bouncing ray/image techniques. By using the impulse responses of these multipath channels, the BER performance of BPSK (binary phase shift keying) system with phase and timing recovery circuits are calculated. Numerical results have shown that the multipath effect by the vehicles in the tunnel is an important factor for BER performance. In addition, the effect of space diversity techniques and decision feedback equalizer on mitigating the multipath fading is also investigated.Chien-Hung Chen was born in Kaohsiung, Taiwan, Republic of China, on 8 March 1971. He received the MSEE degree from Tamkang University in 1999. He is studying for Ph.D. degree in the Department of Electrical Engineering, Tamkang University. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Ching Chiu was born in Taoyuan, Taiwan, Republic of China, on 23 January 1963. He received the BSCE degree from National Chiao Tung University, Hsinchu, Taiwan, in 1985 and MSEE and PhD degrees from National Taiwan University, Taipei, Taiwan, in 1987 and 1991, respectively. From 1987 to1989, he served in the ROC Army Force as a communication officer. In 1992 he joined the faculty of the Department of Electrical Engineering, Tamkang University, where he is now an Professor. He was a visiting scholar at the MIT and University of Illinois, Urbana from 1998 to 1999. His current research interests include microwave imaging, numerical techniques in electromagnetics and indoor wireless communications.Shi-Cheng Hung received the MSEE degree from Tamkang University in 1998. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Hung Lin received the MSEE degree from Tamkang University in 2001. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.     

An Adaptive and Fault-Tolerant Channel Set Allocation Algorithm for Microcell/Macrocell Cellular Networks

Microcell/macrocell architectures are generally deployed in current cellular networks, and involve allocating each cell to a preliminary channel set to support the communications of mobile subscribers. However, cellular networks suffer risks of base transceiver station (BTS) service failure and traffic load variation among BTSs. Both of these conditions impact traffic-carrying capacity and mobile subscriber satisfaction. This investigation presents a dynamic channel set allocation algorithm for ensuring continuous optimization of overall traffic-carrying capacity. This algorithm can tolerate BTSs failure and also resolve the traffic-adaptive problem. Additionally, analytical and simulation results are presented to demonstrate the efficiency of the algorithm.Chyi-Ren Dow was born in 1962. He received the B.S. and M.S. degrees in information engineering from National Chiao Tung University, Taiwan, in 1984 and 1988, respectively, and the M.S. and Ph.D. degrees in computer science from the University of Pittsburgh, U.S.A., in 1992 and 1994, respectively. Currently, he is a Professor in the Department of Information Engineering, Feng Chia University, Taiwan. His research interests include mobile ad-hoc networks, network agents, learning technologies, and embedded systems.Jong-Shin Chen was born in 1972. He received the B.Sc. and Ph.D. degrees in engineering from Feng Chia University, Taiwan, in 1996 and 2003, respectively. His research interests include mobile computing, wireless communications, capacity planning, and systems.Yi-Hsung Li was born in 1979. He received his B.S. degree and M.S. degree in information engineering from Feng Chia University, Taiwan, in 2001 and 2003. He is currently a graduate student for the Ph.D. degree in the Department of Information Engineering and Computer, Feng Chia University, Taiwan. His research interests include personal communications, mobile computing, learning technologies, and network agents.     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail. This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4. Yu-Cherng Hung was born in Changhua, Taiwan, R.O.C., in 1964. He received the M. S. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1992, and the Ph.D. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2004. From Dec. 1986 to Jan. 2005, he was with the Division of Computer/Information, Chinese Petroleum Corp., Taiwan. He is currently an Assistant Professor with the Department of Electronic Engineering, National Chin-Yi Institute of Technology, Taiwan, R.O.C. His main research interests include analog circuit design, low-voltage VLSI design, and neural network applications. Dr. Hung is a Member of Phi Tau Phi Honorary Scholastic Society, IEEE, and the Institute of Electronics, Information, and Communications Engineers (IEICE). Bin-Da Liu received the Ph.D. degrees in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1983. Since 1977, he has been on the faculty of the National Cheng Kung University, where he is currently a Distinguished Professor in the Department of Electrical Engineering and the Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995, he has been a Consultant of the Chip Implementation Center, National Applied Research Laboratories, Hsinchu, Taiwan. He has published more than 200 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). His current research interests include low power circuit, neural network circuit, CMAC neural network, analog neural network architecture, design of programmable cellular neural networks, and very large-scale integration implementation of fuzzy/neural circuits and audio/video signal processors. Dr. Liu is a Fellow of IEEE and the Vice President of Region 10, IEEE Circuits and Systems Society. He served as a CAS Associate Editor of IEEE Circuits and Devices Magazine and an Associate Editor of IEEE Transactions on Circuits and Systems I: Regular Papers. He is serving as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Chung-Yang Tsai was born in Mian-Li, Taiwan, R.O.C. He received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001 and 2003, respectively. His research interests include very large-scale integration design and signal processing.     

Design of Square-Root Domain Filters

In this paper, a square-root domain band-pass filter and biquad filter which are based on the MOSFET square law are proposed. Both of the square-root domain filters operated at 2.5 V supply voltage are constituted by current mirrors, current-mode square-root circuits and capacitors. The circuits presented have been simulated and fabricated using 0.25 m CMOS process. Both of simulation and measured results which are in good agreement indicate that the center frequency f₀ is not only attainable at megahertz frequencies but also tunable electronically. The proposed circuits have the merits of high frequency operation, tuneability, low power supply voltage operation, low third order intermodulation distortion and low total harmonic distortion.Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C.Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000.His current researches include current-mode circuits design, analog IC design and VLSI circuit design.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design.Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively.Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang, Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena, Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits {&} Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.