The case for reconfigurable hardware in wearable computing

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.     

A reconfigurable computing framework for multi-scale cellular image processing

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100× for computationally expensive sub-problems and 10× for end-to-end applications compared to software implementations.     

Portable library development for reconfigurable computing systems: A case study

Portable libraries of highly-optimized hardware cores can significantly reduce the development time of reconfigurable computing applications. This paper presents the tradeoffs and challenges in the design of such libraries. A set of library development guidelines is provided, which has been validated with the RCLib case study. RCLib is a set of portable libraries with over 100 cores, targeting a wide range of applications. RCLib portability has been verified in three major High-Performance reconfigurable computing architectures: SRC6, Cray XD1 and SGI RC100. Compared to full-software implementations, applications using RCLib hardware acceleration cores show speedups ranging from one to four orders of magnitude.     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.     

A process-driven computing model for reconfigurable semiconductor manufacturing

Reconfigurability is essential for semiconductor manufacturing systems to remain competitive. Reconfigurable systems avoid costly modifications required to change and adapt to changes in product, production and services. A fully automated, collaborative, and integrated while reconfigurable manufacturing system proves cost-effective in the long term and is a promising strategy for the semiconductor manufacturing industry. However, there is a lack of computing models to facilitate the design and development of control and management systems in a truly reconfigurable manner. This paper presents an innovative computing model for reconfigurable systems and controlled manufacturing processes while allowing for the integration of modern technologies to facilitate reconfiguration, such as radio frequency identification (RFID) and reconfigurable field programmable gate array (FPGA). Shop floor manufacturing activities are modeled as processes from a business perspective. A process-driven formal method that builds on prior research on virtual production lines is proposed for the formation of a reconfigurable cross-facility manufacturing system. The trajectory of the controlled manufacturing systems is optimized for on-demand production services. Reconfigurable process controllers are introduced in support of the essential system reconfigurability of future semiconductor manufacturing systems. Implementation of this approach is also presented.     

Parallel application performance on shared high performance reconfigurable computing resources

The use of a network of shared, heterogeneous workstations each harboring a reconfigurable computing (RC) system offers high performance users an inexpensive platform for a wide range of computationally demanding problems. However, effectively using the full potential of these systems can be challenging without the knowledge of the system's performance characteristics. While some performance models exist for shared, heterogeneous workstations, none thus far account for the addition of RC systems. Our analytic performance model includes the effects of the reconfigurable device, application load imbalance, background user load, basic message passing communication, and processor heterogeneity. The methodology proves to be accurate in characterizing these effects for applications running on shared, homogeneous, and heterogeneous HPRC resources. The model error in all cases was found to be less than 5% for application runtimes greater than 30 s, and less than 15% for runtimes less than 30 s.     

VHDL语言中断言语句及其综合方法研究

国内外学者普遍认为,硬件描述语言ＶＨＤＬ中断言语句是面向模拟的,其不能综合或不要综合,综合系统应忽略或不支持。本文给出了相反的论点：ＶＨＤＬ中断言语句应该综合,其中限制条件的补表达式可作为随意条件用于综合时化简。文中论述了综合断言语句的合理性,必要性和方便性,并给出了综合并行和串行断言语句的方法。     

A heterogeneous computing system for coupling 3D endomicroscopy with volume rendering in real-time image visualization

Modern microscopic volumetric imaging processes lack capturing flexibility and are inconvenient to operate. Additionally, the quality of acquired data could not be assessed immediately during imaging due to the lack of a coherent real-time visualization system. Thus, to eliminate the requisition of close user supervision while providing real-time 3D visualization alongside imaging, we propose and describe an innovative approach to integrate imaging and visualization into a single pipeline called an online incrementally accumulated rendering system. This system is composed of an electronic controller for progressive acquisition, a memory allocator for memory isolation, an efficient memory organization scheme, a compositing scheme to render accumulated datasets, and accumulative frame buffers for displaying non-conflicting outputs. We implement this design using a laser scanning confocal endomicroscope, interfaced with an FPGA prototyping board through a custom hardware circuit. Empirical results from practical implementations deployed in a cancer research center are presented in this paper.     

适应调试功能的VHDL模型及模拟算法

本文提出一种适应调试功能的ＶＨＤＬ模型及ＶＨＤＬ模拟算法－－－ＶＳＩＭ。它与可视化ＶＨＤＬ原理图输入工具ＶＤＥＳ和高级图形调试器ＶＤＢＸ结合在一起,为设计者检查、修改自己的设计提供了极大的便利。该模拟器采用层次式结构行为混合模型,保存ＶＨＤＬ描述的所有信息和结构,以利于实现调试功能。模拟算法采用基于进程的事件驱动算法及层次式模块调用算法,并提供模拟时间、语句行、模块（包括元件、进程和子程序）、信号     

A programmable spike-timing based circuit block for reconfigurable neuromorphic computing

A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems m CMOS technology to demonstrate the functionality of the circuits in silicon.     

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi- and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

基于不同排序方法的快速霍夫曼编码硬件实现

针对软件霍夫曼静态编码计算量大,而动态霍夫曼编码使得解码器同样复杂的缺点,提出了一种准动态霍夫曼硬件编码器。该编码器每次对一组数据序列进行静态编码,然后将编码并行输出,从而使得编码器具有较高的编码速度,而其延迟时间仅为一次编码过程的总时间。首先,为了充分利用硬件并行特性,分别使用动态排序和静态排序两种排序网络,以适应不同场合的编码需要。然后,使用数据流驱动的硬件二叉树构建和解析结构得到信源符号对应的霍夫曼编码。最后,将储存在FIFO中的输入数据查表并输出。设计结果表明,当使用Nexys4 DDR平台时,该编码器可以工作于100MHz以上的频率,同时具有吞吐高、延迟低、编码效率高和译码器简单的特性。     

Macro-programmable reconfigurable stream processor for collaborative manufacturing systems

Growing demand for high speed processing of streamed data (e.g. video-streams, digital signal streams, communication streams, etc.) in the advanced manufacturing environments requires the adequate cost-efficient stream-processing platforms. Platforms based on the embedded microprocessors often cannot satisfy performance requirements due to limitations associated with the sequential nature of data execution process. During the last decade, development and prototyping of the above embedded platforms has started moving towards utilization of the Field Programmable Gate Array (FPGA) devices. However, the programming of an application to the FPGA based platform became an issue due to relatively complicated hardware design process. The paper presents an approach which allows simplification of the application programming process by utilization of: (i) the uniformed FPGA platform with the dynamically reconfigurable architecture, (ii) a programming technique based on a temporal partitioning of the application in segments which can be described in terms of macro-operators (function specific virtual components). The paper describes the concept of the approach, presents the analytical investigation and experimental verification of the cost-effectiveness of the proposed platform comparing to the platforms based on sequential micro-processors. It is also shown that the approach can be beneficially utilized in collaborative design and manufacturing.     

VLSI设计混合仿真系统的研制

本文介绍了以国际标准硬件描述语言VHDL作输入的VLSI芯片仿真系统的功能及实现策略。该系统将实现全定制式集成电路的版图设计、功能验证和分析等过程。它既可用来辅助VLSI生产，也可以作为模拟实验、教学的实习环境。     

Proteus: A reconfigurable computational network for computer vision

The Proteus architecture is a highly parallel, multiple instruction, multiple data machine (MIMD) optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 gigaflops (80 gigaflops peak). It accepts data via multiple serial links at a rate of up to 640 MB/S. The system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit-switchedenhanced hypercube, serial interconnection network for internal data transfers. The system is designed to use 256 to 1024 RISC processors. The processors use 1-MB externalread/write allocating caches for reduced multiprocessor contention. The system detects, locates, and replaces faulty subsystems using redundant hardware to facilitatefault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling, and development. System software includes a translator for the INSIGHT language, a parallel debugger, lowand high-level simulators, and a message-passing system for all control needs. Image-processing application software includes a variety of point operators, neighborhood operators, convolution, and the mathematical morphology operations of binary and gray-scale dilation, erosion, opening, and closing.     

Design space exploration for partially reconfigurable architectures in real-time systems

In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30 s.     

基于FPGA的卷积码Viterbi编码/译码器的设计与实现

该文设计了一种采用(2,1,2)卷积码的VB编码/解码器,并在Xilinx公司SpartanⅡ-XC2S200 FPGA芯片上实现。所设计的VB编码/解码器具有前向纠错能力强、编解码速度快、占用系统资源少等特点。综合后仿真结果显示,该VB编码/解码器的性能较理想,达到了预期的设计目标。