BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

Full functionality of LSI gate arrays fabricated on 3-in-diameter,MOCVD-grown GaAs-on-silicon substrates

Fully functional, 504-gate arrays have been fabricated on an MOCVD (metalorganic chemical-vapor deposition)-grown, 3-in-diameter, GaAs-on-silicon substrate. Each ECL (emitter-coupled-logic)-compatible gate array consists of an eight-bit adder, a D flip-flop, a 214 divider (with a divide-by-four tap), and a 263-stage inverter string. These circuits represent 90% gate utilization, or approximately 6600 transistors. The wafer-level yield of fully functional gate arrays is 10.7%. This demonstrates total functionality and yield for a digital circuit with LSI-level complexity using MOCVD-grown GaAs-on-silicon material and shows that this material, even with defect densities greater than 108 cm^-2, is viable for high-density LSI circuits     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

Versatile divider circuits up to 9 GHz input-frequency realised in high-speed BICMOS

A versatile divider circuit with three dividing ratios of 2:1, 5:1 and 10:1 was realised in a high speed BICMOS technology, which is characterised by a cut-off frequency of 10.5 GHz and a minimum ECL gate delay time of 50 ps. The maximum input frequencies of the divider circuits are 7.5 and 9 GHz.<>     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

具有有源下拉电路和图腾柱式输出结构的CML门电路

本文提出了一种高速低功耗、具有有源下拉电路和图腾柱式输出结构的ＣＭＬ（简称ＭＣＭＬ）门电路；详细地阐述了ＭＣＭＬ门电路的工作原理和优点；列出了电路仿真结果；并对其电路特性与ＥＣＬ和ＡＰＤ－ＥＣＬ电路进行了比较。     

A high-speed, low-power divide-by-4 frequency divider implementedwith AlInAs/GaInAs HBT's

The authors describe the first frequency divider demonstrated using AlInAs/GaInAs heterojunction bipolar transistors (HBTs). The divider (a static 1/4 divider circuit) operates up to a maximum frequency of 17.1 GHz, corresponding to a gate delay of 29 ps for a bilevel current-mode logic (CML) gate with a fan-out of 2, and a total power consumption of 67 mW (about 4.5 mW per equivalent NOR gate). These results demonstrate the potential of AlInAs/GaInAs HBTs for implementing low-power, high-speed integrated circuits     

A physical hydrodynamic 2D model for simulation and scaling of InP/InGaAs(P) DHBTs and circuits with limited complexity

In this paper we demonstrate a physical two-dimensional hydrodynamic (2D HD) model which simulates the DC and AC characteristics of vertically and laterally scaled InP/InGaAs(P) type I double heterojunction bipolar transistors (DHBTs) with state-of-the-art accuracy when compared to experimental data. For the first time, a physical model clearly shows good agreement between simulated and measured circuit data, for example the gate delay of current mode logic (CML) or emitter coupled logic (ECL) ring oscillators of laterally and vertically scaled devices. The deviation of the simulated gate delays of these digital circuits is smaller than 10%. Additionally, the model successfully predicts the circuit performance of experimental frequency dividers and multiplexers. This experimentally verified model can be used to predict and optimize AC and switching characteristics of future generations of aggressively downscaled DHBTs and is a significant advancement in the art of physical and scalable DHBT and circuit modeling. We demonstrate that optimized type I DHBTs approach bit rates towards 235 Gb/s with realistic scaling parameters in the near future.     

A self-biased feedback-controlled pull-down emitter follower forhigh-speed low-power bipolar logic circuits

A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

An ECL gate with improved speed and low power in a BiCMOS process

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible     

40GHz InGaAs/InP CML 结构静态分频器

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with ...     

Theory of differential current switches and logic design of ternary ECL circuits at switch level

Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional ECL techniques and is compatible with binary ECL circuits.     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

A 150-ps 9000-gate ECL masterslice

A bipolar masterslice chip with an integration level of 9000 gates is described. Internal gate delays down to 150 ps are achieved by utilizing an advanced processiong technology, OXIS III, and a CML circuit technique with three levels of series gating. The 128 mm/SUP 2/ chip has a typical power dissipation of 20 W. I/O levels at 256 logic pins are standard ECL 100 or 10K.     

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2:1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic(CML) with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.     

High-performance implanted base silicon bipolar technology for RFapplications

A 0.4 μm silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above