Challenges of back end of the line for sub 65 nm generation

This paper presents a review of interconnect challenges for sub 65 nm node. From this generation, porous ultra low K (ULK) dielectric materials (dielectric constant k<2.1) are required. Their porosity makes integration very difficult, due to the mechanical weakness and process interaction issues (especially during stripping, CVD metal barrier deposition…). To overcome these process incompatibilities and keep the ‘effective dielectric constant’ low, dual damascene architecture becomes more and more complex and requires additional steps (porosity sealing treatment, degas steps, supercritical CO₂ clean, low k dielectric barrier, self aligned barrier…). Possible contamination trapped in the porosity (moisture, metallic residues…), and lower thermo-mechanical properties of ULK will probably impede reliability. Copper resistivity increase with dimension shrinkage will also be an extra issue.     

Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

A detailed study of copper contaminating steps performed during integration of multilevel Cu metallisation in dual damascene architecture has been performed. Contamination at the wafer back and the bevel edge should make it difficult to use the same equipment for conventional technology and new copper based technology. Several barrier materials have been claimed as efficient against copper diffusion. However, during process integration, contamination issues will be faced before deposition of the barrier layers. Heavy contamination can occur either during Cu chemical mechanical polishing (CMP) or during dielectric etching and via opening on top of contacted copper lines. These residues, concentrated at the dielectric surface, could result in current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencies are compared.     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Characterisation of JSR’s spin-on hardmask FF-02

Some of the spin-on interlayer dielectrics (ILD) with dielectric constant k below 2.3, targeted for the 65 nm node and below, are available with their spin-on hard masks (SoHM) to reduce the total effective capacitance and to provide high selectivity to their respective ILDs during integration. In this work, FF-02, JSR’s SoHM is characterised. Its thermal stability, chemical compatibility to stripping solutions and resistance to moisture are investigated. Methods to seal the surface of FF-02 to chemicals are explored. Electrical properties including the dielectric constant, leakage current and breakdown fields are evaluated in planar capacitors and in single damascene structures.     

Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Air-gaps in 0.3 /spl mu/m electrical interconnections

A copper/air-gap interconnection structure using a sacrificial polymer and SiO/sub 2/ in a damascene process has been demonstrated. The air-gap occupies the entire intralevel volume with fully densified SiO/sub 2/ as the planar interlevel dielectric. The copper was deposited by physical vapor deposition and planarized by chemical-mechanical planarization. The Ta/Cu barrier/seed layer was deposited by physical vapor deposition; the bulk copper was electrochemically deposited. The resulting structure has an effective intralevel dielectric constant of 2.19.     

New solutions for intermetal dielectrics using trimethylsilane-based PECVD processes

Trimethylsilane, (CH₃)₃SiH, is a non-pyrophoric organosilicon gas. This material is easily used to deposit dielectric thin films in standard PECVD systems designed for SiH₄. In addition to deposition of standard dielectrics (e.g. SiO₂), trimethylsilane can be used to deposit reduced permittivity (low-k) dielectric versions of amorphous hydrogenated silicon carbide and its oxides. The low-k carbides (k<5.5) are highly insulating and useful as hard masks, etch stops and copper diffusion barriers. The low-k oxides (2.6<k<3.0) are useful as intermetal dielectrics, and exhibit stability and electrical properties which can meet many specifications in device fabrication that are now placed on SiO₂. This paper reviews PECVD processing using trimethylsilane. Examples will show that the 3MS-based dielectrics can be used in place of SiH₄-based oxides and nitrides in advanced device multilevel metal interconnection schemes to provide improved circuit performance.     

Copper metallization for advanced IC: requirements and technological solutions

Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-k dielectrics and/or low resistivity metals in order to decrease the parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.     

Impact of LKD5109™ low-k to cap/liner interfaces in single damascene process and performance

The importance of interface quality in the single damascene integration process of LKD5109™ porous low-k films is investigated. A strong correlation is observed between chemical mechanical planarization (CMP) performance and LKD/cap layer interfacial fracture energies. The use of FF02™ as cap layer material (an on-purpose developed spin-on organic hard-mask) on LKD leads to superior interfacial adhesion and metal continuity yield as compared to the use of chemical vapour deposition SiC:H cap films. The adhesion quality of LKD/liner films appears less critical than LKD/cap layer adhesion as far as CMP performance is concerned. Electrical line-to-line performance is not always directly correlated with adhesion but rather, more generally speaking, with interface quality (i.e., presence of defects/dangling bonds or moisture). The introduction of surface pre-treatments to enhance interfacial adhesion leads to degradation in both leakage current and breakdown field behaviour because of damage induced at the interface.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Investigation of defect on copper bond pad surface in copper/low k process integration

In this work, inspection tools and surface analysis instruments were used to inspect and to analyze the defects at copper bond pads fabricated with copper/low k dual damascene deep submicron interconnect process integration. The defects at level are believed to be responsible for metal peeling at the Ta + Al and copper interface observed during chip wire bonding operation. The analysis results of the trace defects’ chemical composition show that the trace defects are the remainder of dielectric materials of passivation layer that is deposited on the top of the chip for protection. Copper oxide is also found to be present at the copper bond pads surface. A clear copper bond pad surface could be obtained using optimized dielectric pad window opening plasma etching conditions with suitable level plasma etching power and some overetch, improved photoresist stripping with oxygen and wet clean recipe with some chemicals. A clear copper bond pad surface will contribute to obtainment higher adhesion and lower contact resistance at Ta + Al and copper pad interface.     

Reliability challenges for copper low-k dielectrics and copper diffusion barriers

The performance of interconnects containing micro- (pore size smaller than 2 nm) and meso-porous (pore size larger than 2 nm) interlevel dielectrics is influenced by material selection, integration scheme and virtually all fabrication steps. It is generally reported that the reliability margin of the dielectric/barrier/copper system is shrinking. Barrier and dielectric integrity play a most important role in line-to-line leakage and Time Dependent Dielectric Breakdown (TDDB) reliability. TDDB has never been an issue for Cu-SiO₂ interconnects, but for sub-100 nm copper/barrier/low-k systems it becomes challenging. When monitoring the integrated dielectric properties early failures can be caused by weak integration interfaces, dielectric damage during the integration, defective diffusion barrier or other non-uniformities related to the damascene process. Recent advances are reviewed along with examples and reference to state of the art.     

SILK compatibility with the IMD process using copper metallization

This work presents the results of SILK compatibility with the materials used in the damascene structure with copper metallization. Firstly, the thermal stability of the material was carefully evaluated; excellent stability at 450°C was confirmed. Moreover, 450°C is a good curing temperature for obtaining a low dielectric constant (2.7). The conventional PECVD hard masks, SiO₂ (from SiH₄ or TEOS precursors) and Si_xN_y do not affect the SILK properties. Finally, it was verified that an OMCVD TiN barrier is efficient in preventing copper diffusion. It was demonstrated that SILK should reach the performance requested for IMD materials in the damascene structure with Cu metallization.     

Room temperature electroless plating copper seed layer process for damascene interlevel metal structures

Described in this paper is the development of a room temperature electroless copper seed layer deposition process on ultra-thin TiN barrier layers. This novel process is compatible with damascene interlevel metal structures for sub-0.18 micron ULSI processes. An optimum copper layer thickness of 50 nm and a deposition rate of 45 nm min⁻¹ was targeted and obtained. Atomic force microscopy (AFM) reveals that the non-uniformity of the seed layer is less than 10% of the film thickness, while four-point probe measurements indicate that the resistivity of the copper seed layer is less than 6 μΩ cm⁻¹. Secondary ion mass spectroscopy (SIMS) reveals that potential metallic contaminants such as sodium, potassium, calcium and magnesium ions do not penetrate the TiN barrier layer. Rutherford back scattering (RBS) indicates that the palladium concentration in the seed layer is approximately 1%, which is low enough to avoid wafer contamination and increased resistivity in the subsequent electroplated copper layer.     

A new damascene architecture for high-performance metal–insulator–metal capacitors integration

As high-performance metal–insulator–metal capacitors are required for new technologies, an innovative architecture was developed with standard damascene processes used for copper interconnect realization. Low-cost damascene capacitors were integrated with thin Si₃N₄ films, leading to 2.9 fF/μm² capacitance values and low leakage currents, demonstrating this architecture ability to reduce the insulators thickness, thus achieving high-performance passive implementation for mixed integrated circuits.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Efficiency of reducing and oxidizing ash plasmas in preventing metallic barrier diffusion into porous SiOCH

This work focuses on the efficiency of reducing and oxidizing plasma chemistries in preventing metallic barrier diffusion into porous dielectric materials (SiOCH with a k value close to 2.2, porosity content around 40%). The ash processes have been performed on SiOCH coated blanket and patterned wafers in either reactive ion etching (RIE) or downstream (DS) reactors. The Rutherford backscattering spectroscopy technique (RBS) has shown that titanium based compounds diffuse into the blanket porous SiOCH without treatment during a typical TiN barrier deposition process by chemical vapor deposition (CVD). The metallic barrier diffusion is strongly limited on blanket wafers when the porous SiOCH has been previously modified (partially or fully) by ash plasmas (RIE-O₂, RIE-NH₃, DS-H₂/N₂ and DS-O₂/N₂) while the metallic barrier diffusion occurs with no modifying ash plasmas (DS-H₂/He). We have shown that ellipsometric porosimetry (EP) measurements clearly point out that no complete pore sealing is achieved with all the investigated ash plasmas. Energy-filtering transmission electron microscopy experiments (EFTEM) performed on single damascene structures have revealed significant titanium diffusion into the porous dielectric lines for DS-H₂/He and RIE-O₂ and sidewalls modification of the porous SiOCH lines (lower C/O ratio) for all the ash plasmas. The RC product (resistance × capacitance) have been extracted from the single damascene structures and the evolution of RC product will be discussed in terms of lines modification (titanium diffusion and porous SiOCH modification).     

Reliability of copper low-k interconnects

For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint.     

Ultralow-k silicon containing fluorocarbon films prepared by plasma-enhanced chemical vapor deposition

Low dielectric constant materials as interlayer dielectrics (ILDs) offer a way to reduce the RC time delay in high-performance ultra-large-scale integration (ULSI) circuits. Fluorocarbon films containing silicon have been developed for interlayer applications below 50-nm linewidth technology. The preparation of the films was carried out by plasma-enhanced chemical vapor deposition (PECVD) using gas precursors of tetrafluorocarbon as the source of active species and disilane (5 vol.% in helium) as a reducing agent to control the ratio of F/C in the films. The basic properties of the low dielectric constant (low-k) interlayer dielectric films are studied as a function of the fabrication process parameters. The electrical, mechanical, chemical, and thermal properties were evaluated including dielectric constant, surface planarity, hardness, residual stress, chemical bond structure, and shrinkage upon heat treatments. The deposition process conditions were optimized for film thermal stability while maintaining a relative dielectric value as low as 2.0. The average breakdown field strength was 4.74 MV/cm. The optical energy gap was in the range 2.2–2.4 eV. The hardness and residual stress in the optimized processed SiCF films were, respectively, measured to be in the range 1.4–1.78 GPa and in the range 11.6–23.2 MPa of compressive stress.