Design for testability and built-in self test: a review

A summary is presented of a number of design-for-testability (DFT) and built-in self-test (BIST) schemes that can be used in modern VLSI circuits. The DFT methods presented are used to increase the controllability and observability of the circuit design. Partitioning, bus architectures, test-point insertion, and scan methods are discussed. On-chip hardware for real-time test-pattern generation and data compression are investigated. Several of the DFT methods are then combined to form BIST hardware configurations. Built-in evaluation and self-test (BEST), autonomous test, scan with random inputs, built-in logic block observer (BILBO), partitioning with BEST, test-point insertion with on-chip control, and combined test-pattern generation and data compression (CTGC) are considered. An overview of each BIST scheme is offered     

基于ATPG的无线接入芯片的可测试性设计

可测试性设计是现代芯片设计中的关键环节,针对无线接入芯片的可测试性设计对测试技术有更高的要求。首先概述可测试性设计和测试向量自动生成理论,然后采用最新的测试向量自动生成技术,根据自行设计的无线接入芯片的内部结构及特点,建立一套无线接入芯片可测试性设计的方案。同时功能测试向量的配合使用,使得设计更为可靠。最终以最简单灵活的方法实现了该芯片的可测试性设计。     

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced     

Linking design and test tools: an implementation

A computer-aided test analysis system was designed to appraise the testability of logic systems and to provide the functional specification of the test programs. To provide a helpful tool for both designers and test engineers, it was necessary to fully integrate this tool in a CAD (computer-aided design) system so that testability might be a design parameter and to automate the test-program production. The authors present the link between this tool and the SILVAR LISCO design system     

A language for compositional specification and verification offinite state hardware controllers

The authors consider the state machine language (SML) for describing complex finite state hardware controllers. It provides many of the standard control structures found in modern programming languages. The state tables produced by the SML compiler can be used as input to a temporal logic model checker that can automatically determine whether a specification in the logic CTL is satisfied. The authors describe extensions to SML for the design of modular controllers. These extensions allow a compositional approach to model checking which can substantially reduce its complexity. To demonstrate these methods, the authors discuss the specification and verification of a simple central-processing-unit (CPU) controller     

Clairvoyant: a synthesis system for production-based specification

This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques     

Fundamentals of testability-a tutorial

A review is presented of electrical testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. The relationships between the most commonly used fault models are explored. Various fault simulation methods are contrasted. The basic mechanisms used in test-vector generation are illustrated by examples. The importance of testability analysis as a guide to design and test generation is discussed. Algorithms for automatic test-pattern generation are summarized     

Testability-analysis driven test-generation of analogue cores

A new definition of the testability transfer factor for circuit components that provides better sensitivity with respect to parametric deviations is presented. New equations for the testability measures in a mixed-signal core are given. Testability analysis is used for test-pattern generation and for consideration of inserting wrapper cells. The simulation results show the effectiveness of the approach.     

System Level Design for System on a Chip

We present the systems requirements generation and executable specification capture of a single chip LAN Adapter for communicating using the IEEE 1394 Serial Bus Protocol. The requirements generation starts with high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-existing components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process.     

cfdl语言的设计及其实现

本文介绍一种主要用于描述有限状态机（ＦＳＭ）动作行为及功能设计的硬件描述ｃｆｄｌ是基于对ＦＳＭ行为特性的研究分析，从动作的循环连续有序特点入手，研制开发的一个能抽旬描述ＦＳＭ动作行为和功能的类Ｃ硬件设计描述语言，并且已经编译实现在ＨＰ９０００／３７５工作站上。该语言简单易学，可清晰方便地给出一个可读性好的控制结构设计的描述文本，无二义性，为逻辑设计全面自动化的实现提供了保证。     

High-level library mapping for arithmetic components

We describe high-level library mapping (HLLM), a technique that permits reuse of complex RT-level databook components (specifically ALUs). HLLM can be used to couple existing databook libraries, module generators and custom-designed components with the output of architectural or behavioral synthesis. In this paper, we define the problem of high-level library mapping, present some algorithmic formulations for HLLM of ALUs, and demonstrate the versatility of our approach on a variety of libraries. We also compare HLLM against the traditional mapping approach using logic synthesis. Our experiments show that HLLM for ALUs outperforms logic synthesis in area, delay, and runtime, indicating that HLLM is a promising approach for reuse of datapath components in architectural design and high-level synthesis     

A layout-driven yield predictor and fault generator for VLSI

The authors present an efficient approach to probability-graded fault list generation, and critical area calculation for IC yield production. The approach is also efficient to program because it is built on top of existing design rule checking routines. The accuracy of the tool is enhanced by including in the critical area calculations adjustments for defects occurring at the end of a feature and validating shorts before including the associated critical area in the sum. It would be possible to make the approach more efficient by going to an entirely graph-based approach, thus avoiding the physical tile generation step     

Phase Shifter Merging

Phase shifters are used in conjunction with Linear Feedback Shift Registers and Cellular Automata in order to impose sufficient channel separations on the bit sequences produced by their successive cells. The aim is to reduce structural correlations and/or linear dependencies that are problematic for pseudorandom and pseudoexhaustive built-in test pattern generation (TPG). In this paper we present a synthesis approach that merges the logic of the original TPG mechanism with that of the required phase shifter network and yields a new compact structure that can offer lower area overhead and improved frequency of operation than the existing approach.Dimitri Kagaris received the Diploma degree in Computer Engineering and Informatics from the University of Patras, Greece, in 1988, and the M.S. and Ph.D. degrees in Computer Science from Dartmouth College, Hanover, New Hampshire, in 1991 and 1994, respectively. He is currently an Associate Professor in the Electrical & Computer Engineering Department, Southern Illinois University at Carbondale. His research interests include digital design automation, test pattern generation and design for testability, and computer networks.     

Deterministic built-in test pattern generation for high-performancecircuits using twisted-ring counters

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds     

A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs

This paper describes a design synthesis environment which can generate an efficient VLSI layout from a recursive DSP algorithm specified by a graph. The design synthesis environment is divided into three parts: optimal schedule generation, circuit synthesis, and VLSI layout generation (silicon compilation). The scheduler first computes optimality conditions for a given input algorithm and then finds a schedule which satisfies the optimality conditions. We have employed a cyclo-static optimal multiprocessor compiler as a scheduler. The circuit synthesis component translates the optimal schedule into a structural specification, including the control structures, for an circuit realization. In the final part, a VLSI layout is generated from the structural specification. We have chosen the LAGER system for the silicon compilation. This paper illustrates the design synthesis process with complete details of a simple, complete example, a second order Direct Form II IIR filter.This work was supported in part under the Joint Services Electronics Program Contract # DAAL-03-90-C-0004.