Incorporating testability considerations in high-level synthesis

In this article we propose two novel methods to improve the testability of the designs produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies self-loops in a design generated by a high-level synthesis system and eliminates as many of these loops as possible by altering the register and module bindings. The second method, BINET with test cost, is a binding algorithm that takes the cost of testing into account during the binding phase of the high-level synthesis. The test cost considered in this article is a function of the number of self-loops in the synthesized design. Thus it generates only those solutions that have fewer if any self-loops. Finally we put the two methods together in which we first use BINET with test cost to produce nearly self-loop free designs and we further improve their testability by using the loop-breaking algorithm. We applied these methods to synthesis benchmark circuits and the results of our study, given in this article, show that the designs produced by our method have indeed reduced testability overhead and improved testability.     

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I_DDQ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I_DDQ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I_DDQ -based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general     

Microprocessor testability

As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed for testability). The authors describe the testing problem for microprocessors, including the various methods of generating test sets and their application by the user. A survey of the testability features of some of today's commercially available microprocessors is presented. Suggestions for testability features for future-generation microprocessors are also discussed     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

Analog/digital ASIC design for testability

The author addresses three issues in design for testability (DFT) for mixed analog/digital application-specific integrated circuit (ASIC) chips: controllability, observability, and completeness in testing. These are examined for commonly used analog functions, and the results culminate in an architecture for testable mixed analog and digital circuits. The architecture is designed to solve the problems associated with testing basic circuit configurations for different types of commonly used analog macros. Using the recommended architecture to gain access to control and observation test points in the analog portions of the mixed analog/digital ASIC, a series of analog test tables for several different analog functions have been derived. The analog test procedures are independent of any digital design for testability that might be used in the digital portions of the ASIC. General testing procedures for current analog/digital ASICs are described along with desirable characteristics for testers for this type of circuit     

The economics of scan-path design for testability

In this article, scan design for testability (DFT) methods are categorized based on the percentage of storage elements made scannable. The non-scan element state retention problem that occurs in partial scan design methods, in which not all of the storage elements are implemented as scan elements, is discussed. Solutions to this problem are described and the overheads associated with them are discussed. An economic model that allows the costs of a range of scan methods that differ in the percentage of storage elements made scannable to be compared with each other is presented. It is shown that, for systems produced in low volumes, the adoption of full scan DFT can be more cost-effective than partial scan DFT when life-cycle costs are considered if it results in significant reductions in the time taken to get the product to market.     

Design for testability of embedded integrated operationalamplifiers

The operational amplifier (op amp) is one of the most encountered analog building blocks. In this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless test solution, known as oscillation test, is investigated to test the op amp. During the test mode, the op amps are converted to a circuit that oscillates and the oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some Design for Testability (DfT) rules to rearrange op amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented techniques ensure a high fault coverage with a low area overhead     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

CMOS circuit testability

CMOS circuits present unique testing problems. Although open faults in CMOS circuits can be statistically tested, a sequence of patterns is required to guarantee a test. In addition, connections in the circuit layout affect testability. An automatic test generator has been developed to generate test sequences which will detect open CMOS faults.     

Measures of testability for automatic diagnostic systems

Evaluation models of automatic diagnostic systems are investigated taking into consideration their imperfections such as failure to diagnose, incorrect isolation, false alarms, and inability to duplicate. Three measures of effectiveness are developed that enable the decision-maker to assess accurately the real capability of the diagnostic system and to evaluate and compare the performances of alternative automatic diagnostic systems based on their mean life-cycle cost. Analytic procedures for using these measures are developed, and an example is presented. It is concluded that the capability and performance of automatic diagnostic systems can be assessed using three measures of effectiveness; false removal, failure to diagnose, and false alarm correction. The three measures can be used to predict the mean life-cycle cost of automatic diagnostic systems, including the mean cost of imperfections of such systems     

A fault-tolerant array processor designed for testability andself-reconfiguration

The design of a fault-tolerant rectangular array of processing elements (PEs) is presented in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare PEs are included in every column of the array, and faulty PEs are bypassed within a column to facilitate reconfiguration in the presence of faults. Scan paths are used to enhance the testability of the array. PEs are tested locally using near-neighbor comparisons without the need of an external host. Because the interconnections between logical neighbors are short, the speed penalty for reconfiguration is very small. Any amount of redundancy can be incorporated in the array without changing the topology of the scheme or the design of the reconfiguration switches. The scheme is well suited for very large-area, high-density chips and wafer-scale integration. In order to demonstrate the capabilities of the scheme and evaluate its performance, an experimental chip consisting of a 6×4 array was designed, fabricated, and tested. Details of the design and the implementation of the chip are presented. The scheme is also analyzed for yield and area utilization for a range of array sizes and PE survival probabilities     

Design for testability of analog/digital networks

The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans     

A novel clocking technique for VLSI circuit testability

Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these requirements for certain designs with static flip-flops that are controlled by two independent signals (master clock and slave clock). This is possible because, in normal circuit operation, the master and slave clocks are never simultaneously active. The new clocking structure uses the `all clocks active' condition to specify the scan mode. Implementation of the concept is discussed in detail for two-clock circuits. Single-clock circuits can be modified to use this scheme, and the results for this class of design are also presented.     

Design of CMOS circuits for stuck-open fault testability

A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes     

ARCHGEN: Automated synthesis of analog systems

High-level design of analog systems is an open area that needs to be addressed with the emerging trend of integrating mixed analog-digital systems. Design methods compatible across the analog-digital boundaries would expedite the design process, and in this paper we address analog high-level design issues. An approach for systems-level synthesis of a class of analog systems is presented. A behavioral level for the analog domain is characterized in terms of state equations and transfer functions in the continuous and discrete domains. State-space representations are generated from transfer function specifications that exhibit system level characteristics such as controllability and observability as, well as decoupled and parallel architectures. These state-space representations are synthesized into behavioral-level, technology-independent architectures composed of analog functional components. An intermediate architecture in a circuit implementation technology is synthesized from the behavioral architecture. The various algorithmic procedures for synthesis are implemented in the program ARCHGEN. Behavioral simulation is used for architecture verification and design space exploration     

Module allocation with idle-time utilization for on-line testability

This paper presents a module allocation technique to improve on-line testability of a data path. The technique assigns multi-type operations to modules. Types of modules and count of each type of module, needed to synthesize a given scheduled data flow graph (SDFG) must be known a priori. The testing utilizes idle time of modules. The objective is to test each type of operation assigned to a module. Testing time is reduced by minimizing the number of types of operations assigned to a module. Certain operations called idle-time operations are scheduled in the SDFG and assigned to modules in their idle time to enhance testing. Ideally, one idle-time operation is required for each type of operation assigned to the module. The technique minimizes number of types of operations assigned to each module and creates sufficient idle time. Promising results are obtained on benchmark examples.     

ITA: An algorithm for I DDQ testability analysis

This paper presents the I _DDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of essential vectors to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by levelizing the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and '89 circuits.     

A realistic defect oriented testability methodology for analog circuits

Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.