In situ growth monitoring of AlGaN/GaN distributed Bragg reflectors at 530 nm using a 633 nm laser

The metal-organic chemical vapor deposition(MOCVD) growth of AlGaN/GaN distributed Bragg reflectors (DBR) with a reflection peak at 530 nm was in situ monitored using 633 nm laser reflectometry.Evolutions of in situ reflected reflectivity for different kinds of AlGaN/GaN DBR were simulated by the classical transfer matrix method.Two DBR samples,which have the same parameters as the simulated structures,were grown by MOCVD.The simulated and experimental results show that it is possible to evaluate the DBR...     

Influence of lattice symmetry and hole shape on the light enhanced transmission through the subwavelength hole arrays

The golden films with various subwavelength hole arrays on the film surface are designed and fabricated on glass substrate by electron beam lithograply （EBL）, focused ion beam （FIB）, and reactive ion etching （RIE）, respectively. The influences of the hole array symmetry and the hole shape on the light-enhanced transmission through the films are observed and simulated. The experimental results show that when the array lattice constant and the hole diameter are the same in the different array structures which are 1 μm and 350 nm respectively, the square hole arrays exhibit two transmission peaks at 1170 nm and 1580 nm with the transmissivities of 3% and 6%, respectively, while the hexagonal hole arrays exhibit an enhanced peak of 14% at 1340 nm; when the lattice constant and the duty cycle are the same for different array stucture,.the transmission peaks are different for different hole shapes, which are at 763 nm with transmissivity of 12% for rectangular holes and at 703 nm with the one of 9%, respectively The numerical simulation results by using the transfer matrix method （TMM） are consistent with the observed results.     

A novel orthogonal modulation format of D8PSK/ASK with differential bi-phase encoding and its application in a label switching optical network

The principle of a novel orthogonal modulation format of differential 8-level phase-shift keying amplitude-shift keying (D8PSK/ASK) with differential bi-phase encoding (DBC) is introduced. Based on it, an optical labeling scheme, in which the payload is 100 Gbit/s D8PSK signal and the label is 10 Gbit/s DBC-ASK signal, is proposed and simulated. The results are compared with other current schemes, and the effects of transmission range, modulation extinction ratio (ER) and received power on system performance are analyzed, respectively. The results show that the spectrum efficiency and bit error rate (BER) are improved greatly, and when the modulation ER is increased to 11 dB, the balanced performance between the payload and label is achieved.     

Repair the faulty TSVs with the improved FNS-CAC codec

Through-silicon via (TSV) is a key enabling technology for the emerging 3-dimension (3D) integrated circuits (ICs). However, the crosstalk between the neighboring TSVs is one of the important sources of the soft faults. To suppress the crosstalk, the Fibonacci-numeral-system-based crosstalk avoidance code ( FNS-CAC) is an effective scheme. Meanwhile, the self-repair schemes are often used to deal with the hard faults, but the repaired results may change the mapping between signals to TSVs, thus may reduce the crosstalk suppression ability of FNS-CAC. A TSV self-repair technique with an improved FNS-CAC codec is proposed in this work. The codec is designed based on the improved Fibonacci numeral system (FNS) adders, which are adaptive to the health states of TSVs. The proposed self-repair technique is able to suppress the crosstalk and repair the faulty TSVs simultaneously. The simulation and analysis results show that the proposed scheme keeps the crosstalk suppression ability of the original FNS-CAC, and it has higher reparability than the local self-repair schemes, such as the signal-switching-based and the signal-shifting-based counterparts.     

Growth and characterization of InGaAs/InP p-quantum-well infrared photodetectors with extremely thin quantum wells

High-quality InGaAs/InP quantum wells with ultra-narrow well widths (∼10?) and peak response at 4.55 μm were grown by gas source molecular beam epitaxy. These structures were characterized by cross-sectional tunneling microscopy (XSTM), double-crystal x-ray diffraction (DCXRD), and cross-sectional transmission electron microscopy (XTEM). Based on the structural parameters determined by XTEM, XSTM, and DCXRD, the field dependent photocurrent spectra were simulated using a six-band effective bond-orbital model. The theoretical calculations are in excellent agreement with experimental data. When used to fabricate p-type InGaAs/InP quantum-well infrared photodetectors (QWIPs), and combined with the high responsivity of 8.93 μm n-type InGaAs/InP QWIPs, these structures offer the possibility of dual band monolithically integrated QWIPs.     

Small Signal Circuit Model of Double Photodiodes

The transmission delay of photogenerated carriers in a CMOS- process- compatible double photodiode (DPD) is analyzed by using device simulation. The DPD small signal equivalent circuit model which includes transmission delay of photogenerated carriers is given. From analysis on the frequency domain of the circuit model the device has two poles. One has the relationship with junction capacitance and the DPD‘s load, the other with the depth and the doping concentration of the N-well in the DPD. Different depth of the Nwell and different area of the DPDs with bandwidth were compared. The analysis results are important to design the high speed DPDs.     

硅通孔中含有加速剂的电镀铜仿真

Filling high aspect ratio through silicon vias(TSVs) without voids and seams by copper plating is one of the technical challenges for 3D integration. Bottom-up copper plating is an effective solution for TSV filling. In this paper, a new numerical model was developed to simulate the electrochemical deposition(ECD) process, and the influence of an accelerator in the electrolyte was investigated. The arbitrary Lagrange-Eulerian(ALE) method for solving moving boundaries in the finite element method(FEM) was used to simulate the electrochemical process. In the model, diffusion coefficient and adsorption coefficient were considered, and then the time-resolved evolution of electroplating profiles was simulated with ion concentration distribution and the electric current density.     

Security performance analysis and the parameters simulation of quantum virtual private network based on IPSec protocol

Traditional virtual private networks (VPNs) are conditional security. In order to ensure the security and confidentiality of user data transmission, a model of quantum VPN based on Internet protocol security (IPSec) protocol is proposed. By using quantum keys for key distribution and entangled particles for identity authentication in the network, a secure quantum VPN is relized. The important parameters affecting the performance of the VPN was analyzed. The quantitative relationship between the security key generation rate, the quantum bit error rate (QBER) and the transmission distance was obtained. The factors that affect the system throughput were also analyzed and simulated. Finally, the influence of the quantum noise channel on the entanglement swapping was analyzed. Theoretical analysis and simulation results show that, under a limited number of decoy states, with the transmission distance increased from 0 to 112.5 km, the secure key generation rate was reduced from 5.63×10^-3 to1.22×10^-5 . When the number of decoy states is fixed, the QBER increases dramatically with the increase of the transmission distance, and the maximum reaches 0.393. Analysis shows that various factors in communication have a significant impact on system throughput. The generation rate of the effective entanglement photon pairs have decisive effect on the system throughput. Therefore, in the process of quantum VPN communication, various parameters of the system should be properly adjusted to communicate within a safe transmission distance, which can effectively improve the reliability of the quantum communication system.     

The Investigation on Single Event Function Failure for DC/DC Converters with Three Single Terminal Topological Structures

Heavy ion radiation experiments have been done to DC/DC converters with different topological structures for space applications.The test results were analyzed about the function failure of three topological structures caused by single event effects.The relationship between the function failure and the input supply voltage,the output load current and the topological structure of the module were discussed.Based on the analysis of the variation relationship among the source/drain terminal voltage of MOSFETs and the input voltage and the output load,the sensitivity factors associated with the function failure caused by single event effects were discussed.A new analysis on single event function failure of DC/DC converter based on different topologies has been presented,which can be applied to radiation hardened design and space application.     

Effect of Electron Drag on Performances of Carbon Nanotubes as Flow Sensors

Experimentally, the electron drag effect on carbon nanotube surface in flowing liquids was investigated. It was found that electric current could be generated in metallic carbon nanotubes immersed in the liquids. Carbon nanotubes were synthesized on Si substrate by hot filament chemical vapor deposition. The experimental results showed that the flow--induced current on the surface of carbon nanotube films was closely depended on the flow rate, concentration, properties and temperature of liquids. The flow--induced current was increased with the increasing of flow rate, concentration and temperature of liquids. The obtained results were discussed in detail.     

Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

The development of effective model for thermal conduction analysis for 2.5D packaging using TSV interposer

The effective model for the orthotropic TSV (Through Silicon Via) interposer in heat conduction for 2.5D IC integration was proposed in this study. The simple parallel model was used in out-of-plane direction to predict the effective thermal conductivity for the TSV interposer. The in-plane effective thermal conductivity for the interposer was derived on basis of heat balances. By introducing the effective orthotropic thermal parameters, the TSV structures can be ignored in the present effective model. The computations using the effective model for TSV interposer and the 2.5D package with interposer were carried out. The results showed that the accuracy of the effective model was above 95% comparing with the real model including TSV structures when the volume ratio of the electroplating copper and the silicon interposer is smaller than 10%. Using the effective model, the parametric studies on the interposer sizes and the thermal conductivities of different materials in the 2.5D package were conducted with higher efficiency. The results showed that the performance and sizes of EMC (Epoxy Molding Compound) and the package substrate are more important than that of internal underfills in heat dissipation of the package with TSV interposer.     

Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

A multistrata dynamic random access memory (DRAM) vertically integrated with a complementary metal oxide semiconductor (CMOS) logic device using through-silicon vias (TSVs) and a unique interposer technology was developed for high-performance, power-efficient, and scalable computing. SMAFTI (SMArt chip connection with FeedThrough Interposer) technology, featuring an ultra-thin organic interposer with high-density feedthrough conductive vias, was used for interconnecting the three-dimensionally stacked DRAM and the CMOS logic device . A DRAM-compatible TSV manufacturing process was realized through the use of a “via-first” process and highly doped poly-Si TSVs for vertical traces inside memory dice. A multilayer ultra-thin die stacking process with micro-bump interconnection using a solid-liquid interdiffusion technique was also developed. The thermal aging reliability of the micro-bump interconnection was evaluated by a unique analysis method and its basic reliability was confirmed. Finally, we fabricated a prototype package including stacked DRAM and a CMOS logic device, and observed the combined operation. High-speed 3 Gbit/s signals were successfully transmitted through the fine interposer between the memory and logic.      

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.     

Mechanical and Electrical Reliability Assessment of Stacking of Ultrathin Chips on Si Interposer Using Back-to-Face Architecture

Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elasto-plastic behavior on the induction of stress in 3D crystalline silicon (Si) systems incorporating Cu through-silicon vias (TSVs). Using a linear isotropic hardening model, simulations of thermal annealing cycles in Cu TSVs indicate that, for sufficient anneal temperatures, plastic yield within the Cu leads to substantial residual stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed with experimental Raman microscopy measurements of post-anneal stress profiles in Si near isolated 5 × 25 μm cylindrical TSVs on a 300 mm Si wafer. Simulations were expanded to investigate the impact of Cu plasticity (yield stress and tangent modulus) on the residual stress profile in Si near isolated TSVs and linear TSV arrays. The results show that the magnitude and extent of the TSV-induced stress field in Si is a non-monotonic function of Cu yield stress. Moreover, the tensile or compressive nature of TSV-induced stress within and outside linear TSV arrays is also a strong function of the Cu yield stress. The simulated impact of Cu tangent modulus on TSV-induced stress in Si is less substantial. The implications of these results for TSV layout with respect to active device placement in a 3D system are discussed.     

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a “mechanical-caulking” technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve ${rm SiO}_{2}$ etching with shorter turn around time (TATs) and high TSV yields of more than 99%.      

The Thermal Stress Analysis for IC Integrations with TSV Interposer by Complement Sector Models

The thermal stress of typical integrated circuit (IC) integration with the interposer of through silicon via (TSV) was investigated in this study. To overcome the huge computational costs due to meshing the large amount of TSVs’ microstructures, a simplified method, i.e. the complement sector model, was proposed and verified by the symmetric 1/8th full model. Using the sector model, the parametric studies were carried out to reveal the critical locations of TSV and the crucial parameters. Furthermore, statistical methods were invoked to clarify the impact of the major parameters, such as the modulus and coefficient of thermal expansion of underfill materials, the pitch and diameter of TSV, etc. Upon the analysis results, the design of minimized stress in TSV for the IC integration with TSV interposer was achieved.