Design of the CMOS low power sub-sampler with integrated filtering for the internet of things

To solve cost and power consumption problems of wireless communication of the internet of things (IoT), a CMOS low power sub-sampler with filtering is proposed. Based on the subsampling theory, the sub-sampler adopts the clock signal with the high sampling ratio to achieve the passive subsampling mixer. It incorporates the sampling switches and capacitors directly into the parallel resonant output load of the balun low noise amplifier (balun-LNA) to form the bandpass filter, which reduces noise folding to improve the noise figure. And with the integrated balun-LNA instead of the off-chip balun it generates the differential signal, which achieves high integration and low power consumption of the system. For the application of IoT wireless communication, the sub-sampler is implemented and simulated based in the UMC 65nm CMOS process. The results show that it can achieve the subsampling frequency down-conversion at the sensitivity of -90dBm by using the clock sampling frequency of 41MHz operating at the central frequency of 780MHz, which acquires a high sampling ratio and better out-band rejection, and its current consumption is 1.6mA at the 1.2V voltage supply. In addition, the proposed sub-sampler chooses the proper sampling frequency to achieve the frequency conversion flexibly, based on different RF signal frequencies.     

环境WiFi能量采集系统的匹配网络与整流电路设计

设计了一款针对WiFi信号的环境能量采集系统,工作频率范围从2.4 GHz到2.485 GHz.该系统采用了4倍压整流电路,并设计了从天线到整流电路的宽带匹配电路,提升了能量采集的效率.设计的宽带匹配电路在WiFi工作频率范围内,S_(11)均小于-10 dB.整流电路可将采集信号增加4倍,能有效提高RF-DC转换效率.测试结果表明,所设计的电路达到了设计要求,在-10 dBm的输入功率下,达到了40%的RF-DC转换效率,并使超级电容在30 min内采集到了257 mV的电压.     

CMOS低噪声放大器Miller效应分析与噪声优化

根据反馈分解理论将晶体管栅漏电容分解等效到放大器输入输出两端,研究了栅漏电容对低噪声放大器(LNA)输入阻抗和噪声系数的影响.基于分析结果对阻抗及噪声公式进行了修正,提出功耗约束条件下的LNA噪声优化方法.设计的2.4 GHz LNA基于中芯国际(SMIC) 0.18 μm RF CMOS工艺,版图后仿结果表明：在1.2 V的工作电压下,该低噪声放大器直流功耗仅为2.4 mW,噪声系数为1.0 dB,功率增益为16.3 dB,输入输出反射损耗均小于-22 dB,三阶互调点IIP3为-3.2 dBm.相比已有的设计,根据修正公式设计的LNA在功耗、输入阻抗匹配、噪声系数等性能指标上有较大的改善.     

毫米波宽带集成本振混频组件的研究

介绍了一种结构紧凑的一体化混合集成本振混频组件和工程设计方法。该组件由具有机械调谐功能的鳍线耿氏振荡器与采用简化鳍线一微带魔T结构制作的单平衡混频器连接构成。设计制作的工程样品在Ka频段的测试指标为:本振工作在35 GHz,射频在26.5~40 GHz的频率范围内变化时,组件的变频损耗为4.7~9.5dB:中频选定为100MHz,射频随本振在33~37GHz的4GHz机调带宽内变化时,组件的变频损耗为4.9~6.2dB。     

2.4GHz线性功率放大器的分析与设计

该文介绍了基于SMIC 0.18μm CMOS工艺工作于2.4GHz功率放大器的设计方法,并给出了仿真结果.电路采用两级放大的结构,驱动级采用自偏置Cascode结构,为了保证驱动级有足够的线性度,偏置电压采用了自适应结构,使偏置电压随着输入功率的不同而变化,保证了放大器的线性度并提高了功率附加效率,功率级采用共源结构...     

一种低功耗CMOS并行双频低噪声放大器

基于SMIC 0.18μm 1P6M CMOS工艺,设计实现了一种低功耗单端输入转差分输出的并行双频低噪声放大器。采用带有源级电感负反馈的共源共栅结构,在功耗限制下在双频段对输入阻抗和噪声性能同时进行优化,实现并行接收,并具有单端输入转差分输出的功能。该低噪声放大器核心电路尺寸为450μm×350μm。仿真表明,低噪声放大器(LNA)在1.227GHz和1.575GHz工作频率处的输入回波损耗分别为-11.61dB和-12dB,功率增益分别为14.67dB和12.68dB,噪声系数分别为2.3dB和2.53dB,输入l dB压缩点分别为-18.5dBm和-14.5dBm。在1.8V电源电压下,功耗仅为8.4mW,可用于航空航天领域的电子系统中。     

基于变压器反馈的平坦噪声系数超宽带CMOS低噪声放大器

在系统中集成超宽带(UWB)收发机芯片用于支持室内定位正成为移动通信终端技术发展的一个重要趋势.在超宽带收发机中,低噪声放大器(LNA)是一个核心功能模块.超宽带的全频段(3.1～10.6 GHz)覆盖要求给低噪声放大器的设计带来了巨大挑战,尤其是需要在宽带匹配及在带内维持平坦的噪声系数的情况下.传统的低噪声放大器架构...     

Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

A 1 kbit antifuse one time programmable (OTP) memory IP, which is one of the non-volatile memory IPs, was designed and used for power management integrated circuits (ICs). A conventional antifuse OTP cell using a single positive program voltage (V _PP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time, securing the reliability of medium voltage (V _M) devices that are thick gate transistors. A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop. For the newly proposed cell, a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse. The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek’s 0.18 μm Bipolar-CMOS-DMOS (BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.     

低电压、高PSRR的带隙电压基准源

设计了一款高精度、低电源电压的CMOS带隙基准源,具有良好的电源抑制比。电路采用电流模结构和反馈控制实现了低电压、低功耗和高电源抑制比。基于0.25μm CMOS工艺,测试结果表明:在1V电源电压下,1KHz频率时,电源抑制比约为80dB,在0-70℃温度范围内,输出电压变化率不超过0.3%。     

Ka频段微带四次谐波混频器

介绍了一种Ka频段的微带四次谐波混频器的混频原理和设计方法。该混频器主要由波导-微带过渡,输入、输出滤波器以及匹配网络和反向并联混频二极管对组成。根据计算机辅助设计软件的仿真结果,在介电常数为2.22,厚度为0.254 mm的RF-Duroid 5880介质基片上制作了电路。当射频频率为34.2~35.2 GHz,本振频率为8.525~8.775 GHz,中频频率为100 MHz时,测得的变频损耗小于10.5 dB,其中最佳值为8.5 dB。     

0.18 μm CMOS高效高增益功率放大器设计

在自偏置A类共源共栅射频功率放大电路拓扑基础上,基于SMIC 0.18 μm CMOS工艺设计了两级自偏置A类射频功率放大器电路.该射频功率放大器电路采用两级共源共栅结构,在共栅MOS管上采用自偏置.采用Cadence公司的SpectreRF工具对电路进行仿真与优化.设计与优化结果表明,在2.4GHz频率下,输出功率为20.3dBm,功率附加效率为49％,功率增益达到32dB.     

应用于802.11a的5.8 GHz CMOS LNA设计

采用0.18μmCMOS工艺设计应用于802.11aWLAN的5.8GHzLNA.,给出了采用ADS的模拟结果:在中心频率5.8 G Hz处,LNA功率增益为16.97dB,阻抗匹配系数S11小于-18dB,噪声系数(NF)为2.3dBm,输入1dB压缩点为-23.33dBm.输出1dB压缩点为-7.361dBm,功耗小于15mW.     

兼容5G毫米波n257和n258频段的氮化镓低噪声放大器设计研究

基于100 nm的氮化镓(Gallium Nitride, GaN)高电子迁移率晶体管(High Electron Mobility Transistor, HEMT)工艺设计了一款毫米波低噪声放大器(Low Noise Amplifier, LNA)单片式微波集成电路(Monolithic Microwave Integrated Circuit, MMIC)芯片。该款低噪声放大器采用三级级联的拓扑结构,对带宽、噪声和增益进行了联合优化设计。测试结果显示,工作频率范围覆盖24～30 GHz,可兼顾5G毫米波n257(26.5～29.5 GHz)和n258(24.25～27.5 GHz)频段,噪声系数可达到2.4～2.5 d B的水平,小信号增益在21.1～24.1 d B之间,输出1 d B功率压缩点大于14.4 d Bm的水平。     

基于65-nm CMOS工艺的W波段两路电流合成型功率放大器的设计

采用三级差分共源结构设计了一种基于65-nm CMOS工艺的W波段功率放大器,并利用两路电流型功率合成结构进行功率合成以提升输出功率.为了同时实现单差分转换、阻抗匹配、直流供电,匹配网络采用变压器结构.仿真结果显示,在1V的电源电压下,该功率放大器的小信号增益为12.7～15.7 dB,3?dB带宽为84～104 GH...     

应用于北斗接收机的低噪声放大器设计

该文采用电容交叉耦合技术,设计了基于SMIC0.18μm CMOS工艺的应用于北斗二号接收机全差分低噪声放大器,中心频率为1 561.098MHz。仿真结果表明：该低噪放的噪声系数为2.045dB,功率增益S21为19.684dB,输入反射系数S11和输出反射系数S22分别小于-13dB和-40dB,反向隔离S12小于-40dB,线性度IIP3大于-5.5dBm,在1.8V电压下的总功耗为16mW。     

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

The direct current-direct current (DC-DC) converter is designed for 1 T static random access memory (SRAM) used in display driver integrated circuits (ICs), which consists of positive word-line voltage (V _PWL), negative word-line voltage (V _NWL) and half-V _DD voltage (V _HDD) generator. To generate a process voltage temperature (PVT)-insensitive V _PWL and V _NWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a V _PWL regulator and a V _NWL charge pump were proposed for a small-area and low-power design. The proposed V _PWL regulator can provide a large driving current with a small area since it regulates an input voltage (VCI) from 2.5 to 3.3 V. The V _NWL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to V _NWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.     

一款低电压高精度CMOS运算放大器设计

设计了一种采用0.6um CMOS工艺的低电压高精度的运算放大器电路。在设计中输入级采用两对跨导器件rail-to-rail的电路结构,从而实现输入级的跨导在整个共模输入范围内保持恒定。输出级采用AB类rail-to-rail推挽结构,达到高驱动能力和低谐波失真的目的。此运放可提供1.5V电压降,采用适当的输出负载,闭环电压增益,单位增益带宽和相位裕度分别达到了80dB,832kHz和64°。     

基于双电压和倍频技术的低功耗高效率发射机

为了克服电池容量的局限性,延长芯片的待机时间,针对传统发射机的高功耗、低效率问题,提出新型发射机架构. 采用2级注入锁定环形振荡器提供多相信号,电荷泵自举升压电路对该多相信号进行电压提升,实现低电压低功耗设计. 边沿合成器对多相信号进行倍频,使前级电路工作在低频,降低系统功耗. 基于55 nm CMOS工艺,设计433 MHz ISM频段发射机进行验证. 仿真结果表明,发射机的输出功率为?9.7 dBm,环形振荡器和电荷泵自举升压电路工作在0.6 V电源电压下,边沿合成器工作在1.2 V电源电压下,发射机整体功耗为357.04 μW,效率为29.83%,版图面积为70 μm×100 μm. 实验结果证明,所提结构具有功耗低、效率高、面积小和复杂度低的优点.     

Fully-Differential Multichannel Integrated Neural Signal Recording Front-End

Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-channel fully-differential neural recording chip is designed.The chip consists of 16-channel low-noise pre-amplifiers,a multiplexer and a successive approximation register(SAR)ADC.The result shows that the equivalent input-referred noise of recording amplifier is 3.63μV,bringing down noise efficiency factor to 4.24.At 8.5 bits effective number of bit(ENOB),the analog-to-digital converter(ADC)has an SNR of 52.6dB.The core area of the proposed neural recording front-end is about 2.46 mm~2.     

2.4GHzChirp发射机射频前端的设计与实现

为了能在2.4 GHz频段实现有效通信,将Chirp扩频技术应用于2.4 GHz ISM频段,利用其良好的抗噪性能,设计了多带Chirp发射机。同时,研究了Chirp发射机射频前端的参数指标和制作要点,并使用 ADS对系统方案进行了增益预算仿真。在单个子带通信时对系统性能进行了测试,结果表明,设计的发射机射频前端发射功率为15 dBm,带内平坦度小于1 dB,杂散及谐波抑制度好,满足视距高速无线数据传输的要求。