Failure mechanisms of IGBTs under short-circuit and clampedinductive switching stress

The application of insulated gate bipolar transistors (IGBTs) in high-power converters subjects them to high-transient electrical stress such as short-circuit switching and turn-off under clamped inductive load (CIL). Robustness of IGBTs under high-stress conditions is an important requirement. Due to package limitations and thermal parameters of the semiconductor, significant self-heating occurs under conditions of high-power dissipation, eventually leading to thermal breakdown of the device. The presence of a parasitic thyristor also affects the robustness of the device. In order to develop optimized IGBTs that can withstand high-circuit stress, it is important to first understand the mechanism of device failure under various stress conditions. In this paper, failure mechanisms during short-circuit and clamped inductive switching stress are investigated for latchup-free as well as latchup-prone punchthrough IGBTs. It is shown that short-circuit and clamped inductive switching cannot be considered equivalent in the evaluation of a device safe operating area (SOA). The location of thermal failure of latchup-free punchthrough IGBTs is shown to be different for the two switching stresses     

Temperature behavior and annealing of insulated gate transistors subjected to localized lifetime control by proton implantation

Localized lifetime control by proton implantation can result in a considerable improvement in the trade-off between device turn-off time and forward voltage when compared with the unlocalized method of electron irradiation. After a proton dose of 3 × 10¹¹cm⁻² at 3.1 MeV implanted here into insulated gate transistors, turn-off time is reduced by more than an order of magnitude compared to unimplanted devices. When the implanted devices are operated as high voltage switches at a current of 152 A cm⁻² and at a forward blocking voltage of 400 V, the following increases are observed by increasing device operating temperatures from 20 to 150°C, (a) forward voltage: 2.5 V to 2.7 V; (b) turn-off time: 0.78 μs to 1.23 μs; (c) leakage current: 20 nA to 1 mA. The physical mechanisms responsible for the qualitative temperature dependences are identified: MOS channel resistance for forward voltage, carrier capture cross-section for turn-off time, and generation and diffusion components of leakage current. Since no catastrophic or unrecoverable behavior is observed, normal device operation within the tested temperature range is possible. Isothermal annealing curves of turn-off time measured after annealing, and corresponding to a few hours annealing time, reveal that a constant turn-off time is reached after about an hour. The constant value increases with temperature, but is still below the unimplanted value after 4 h at 525°C. The turn-off time was verified to be constant even after 24 h of annealing at 200°C. Lifetime control by proton implantation seems to be more thermally stable than that caused by electon irradiation.     

Investigation on damaged planar-oxide of 1200 V SiC power MOSFETs in non-destructive short-circuit operation

The purpose of this paper is to present an extensive study of three 1200 V silicon carbide (SiC) Power MOSFETs in non-destructive, but leading to degradations, short-circuit operation. Unusually, as compared with equivalent device built on silicon, the damage signature is a significant gate current increase but the components are still functional. In order to find the damage location, non-destructive and destructive methods have been carried out. The results converge to a local gate oxide breakdown caused by the important electrical and thermal stress during short-circuit operation leading to different failure mechanisms depending on the device design.     

Temperature dependence of field-controlled thyristor characteristics

The dependence of the characteristics of field-controlled thyristors upon the ambient temperature has been examined in the range of -30 to 200°C. Unlike conventional thyristors, these devices have been found to continue to exhibit forward blocking capability up to the highest measurement temperature (200°C). In fact, it is shown here that the forward blocking capability as well as the blocking gain improve with increasing temperature with the usual scaling of the leakage current for power devices. The reverse blocking capability is also retained. The forward voltage drop of the device in the conducting state decreases with increasing temperature. This behavior is shown to be similar to that of conventional rectifiers and thyristors operated at high injection levels. Further, the force gate turn-off time of the devices has been found to increase with increasing temperature. This has been correlated with a measured increase in the minority-carrier lifetime. The results of this study demonstrate that field-controlled thyristors are capable of being operated at higher temperatures than conventional thyristors.     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

Comparison of 300-, 600-, and 1200-V n-channel insulated gate transistors

The performance of insulated gate transistors with 300-, 600-, and 1200-V ratings were experimentally investigated. A comparison of several device characteristics, such as forward conduction, forward drop versus turn-off time tradeoff, and the dependence of turn-off time and leakage current upon electron irradiation dosage, is provided.     

Electron irradiation of field-controlled thyristors

The influence of 3-MeV electron irradiation upon the characteristics of asymmetrical field-controlled thyristors has been examined for fluences of up to 16 Mrad. In addition to the lifetime reduction due to the radiation damage, carrier removal effects have also been observed in the very lightly doped n-base region of these devices. The leakage current, even after radiation at the highest fluenee, is not significantly increased and the blocking characteristies of these devices are not degraded. In fact, a small improvement in the blocking gain has been observed at low gate voltages. The electron irradiation has been found to increase the forward voltage drop during current conduction and to reduce the forced gate turn-off time. Gate turn-off times of less than 500 ns have been achieved by irradiation with a fluence of 16 Mrad. However, this is accompanied by a large increase in the forward voltage drop. Tradeoff curves between the forward voltage drop and the gate turn-off time have been obtained. From these curves, it has been determined that gate turnoff times of 1 µs can be obtained without a significant increase in the forward voltage drop for devices capable of blocking up to 600 V.     

Turn-off failures in individual and paralleled MCT's

A turn-off failure mode in individual MOS-controlled thyristors (MCTs), initiated by a long gate voltage rise-time, is identified and analyzed. It is shown to be caused by turn-off current crowding in the MCT. In addition, a differential failure mode in paralleled devices is demonstrated in which the slower of the two MCTs fails to turn off. This is caused by the increase in anode current through the slower device and the decrease in gate voltage rise-time due to the MCTs Miller capacitance     

IGBT关断瞬态电压尖峰影响及抑制

绝缘栅双极晶体管(IGBT)是一种性能优良的全控型电力电子器件,由于线路和器件内部分布电感的存在,关断时集电极电流的快速变化会感应产生一个较大的电压尖峰从而引起过电压击穿。分析了栅极结电容放电时间常数和拖尾电流对电压尖峰的影响,通过改变栅极驱动电阻和温度可以抑制电压尖峰。分析了电压尖峰引起过压击穿的失效机理以及失效模式,表明IGBT过压击穿引起失效的本质仍然是结温过高引起的热击穿失效。     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.     

Overload robust IGBT design for SSCB application

This paper presents an optimised power semiconductor architecture based on the CIGBT approach to be used in solid-state circuit breaker (SSCB) applications where the conduction losses have to be as low as possible without compromising the forward voltage blocking capability. Indeed, a high overcurrent turn-off and short-circuit withstand capabilities have to be ensured. Starting from a standard NPT-IGBT design for switching applications, the results show that the proposed device, which is optimised by the application of the individual clustered concept, offers a reduction in conduction losses of 13%, without compromise on voltage blocking capability. An original design solution is implemented to further ensure short-circuit and overload turn-off capabilities at maximum ambient temperature and twice the nominal rated current.     

Operation of SiC normally-off JFET at the edges of its safe operating area

The paper presents the results of an experimental characterization about the operation of the last-generation normally-off SiC JFETs at the edges of their safe operating area. Short circuit and unclamped turn-off operations have been investigated by means of a nondestructive experimental set up where the device is switched in the presence of a protection circuit capable of limiting the energy dissipated on the device after the failure occurrence. The experimental results confirm the very good performances of the device in short circuit for which the failure can be associated only to the increase of the temperature over the limits imposed by the surface metallization. A different scenario appears for the unclamped tests where a second breakdown occurs after a quite long avalanche phase followed by the device failure. It is demonstrated that the duration of the avalanche phase depends on the temperature of the device under test. The damaged area after an avalanche failure is localized at the edge termination of the device and, in particular, at the corner between source and gate metallization.     

横向电阻区对IGBT过电流关断能力的影响研究

针对绝缘栅双极晶体管(IGBT)在过电流关断测试中被烧毁的问题,设计了三种不同的横向电阻区结构。为了分析器件的失效机理,研究不同结构横向电阻区对过电流关断能力的影响,借助Sentaurus TCAD仿真工具构建了器件模型,模拟了器件的整个过电流关断过程。对三种结构器件在过电流关断过程中的内部关键物理参量的变化情况进行分析,发现不同长度的横向电阻区对空穴的抽取效率不同,进而可以影响到电流密度分布。当电阻区增加到一定长度时,可以有效提升过电流关断能力,避免器件烧毁失效。     

The MOS depletion-mode thyristor: a new MOS-controlled bipolarpower device

A new MOS-bipolar power device in which forced-gate turn-off is achieved using a depletion region formed by an MOS gate structure is described. This device, called the depletion-mode thyristor (DMT), offers many highly desired features for high-voltage power switching applications: a) low ON-state drop, b) high input impedance, c) three-terminal operation, d) equivalent complementary devices, and e) high maximum controllable current. Experimental verification of device operation has been achieved using a UMOS gate technology     

Trench IGBT failure mechanisms evolution with temperature and gate resistance under various short-circuit conditions

Two extreme configurations under short-circuit conditions leading to the punch through trench IGBT failure under the effect of the temperature and the gate resistance have been studied. By analyzing internal physical parameters, it was highlighted that the elevation of the temperature causes an acceleration of the failure which is due to a thermal runaway phenomenon, whereas the influence of the gate resistance on the failure evolution is minimal.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

Structure oriented compact model for advanced trench IGBTs without fitting parameters for extreme condition: Part II

Compact model for expressing turn-off waveform for advanced trench gate IGBTs is proposed even under high current density condition. The model is analytically formulated only with device structure parameters so that no fitting parameters are required. The validity of the model is confirmed with TCAD simulation for 1.2–6.5 kV class IGBTs. The proposed turn-off model is sufficiently accurate to calculate trade-off curve between turn-off loss and saturation collector voltage under extremely high current conduction, so that the model can be used for system design with the advanced trench gate IGBTs.     

A high-current and high-temperature 6H-SiC thyristor

A 6H-SiC thyristor has been fabricated and characterized. A forward breakover voltage close to 100 V and a pulse switched current density of 5200 A/cm² have been demonstrated. The thyristor is shown to operate under pulse gate triggering for turn-on and turn-off, with a rise time of 43 ns and a fall time of less than 100 ns. The forward breakover voltage is found to decrease by only 4% when the operating temperature is increased from room temperature to 300°C. It is found that anode ohmic contact resistance dominates the device forward drop at high current densities     

High temperature performance and operation of HFETs

The high temperature performance of Al_0.75Ga_0.25 As/In_0.25Ga_0.75As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500°C. Both experimental and modeled devices have shown acceptable digital characteristics to 400°C. Digital logic circuits have also been shown to operate at temperatures of over 400°C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400°C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not