A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.     

An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2

This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application, which is fully compatible with standard digital CMOS technology. A modified MOS-transistor-only folding block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 μm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm².     

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.     

一种8位100 MS/s的低功耗流水线型ADC

基于0.35 μm CMOS工艺,设计并制作了一种低功耗流水线型ADC。分析了ADC结构对功耗的影响,采用1.5位/级的流水线结构来最小化功耗,并提升速度。为进一步降低功耗,设计了一种不带补偿并可调节相位裕度的共源共栅跨导放大器(OTA)和改进的比较器。测试结果显示,该ADC在3 V电源电压、100 MS/s采样速率下,功耗为65 mW,面积为0.73 mm²,在模拟输入频率为70.1 MHz和141 MHz下的无杂散动态范围(SFDR)分别为59.8 dBc和56.5 dBc。该ADC可应用于需要欠采样的通信系统中。     

一种用于12位250MSPS流水线ADC的中频采样前端

设计了一种具有中频采样功能的流水线ADC采样保持前端电路.采样保持前端电路采用基于开关电容的底板采样翻转式结构,运算放大器采用了米勒补偿型两级结构以提高信号摆幅,采样开关采用了消除衬底偏置效应的自举开关以提高中频采样特性.该采样保持前端电路被运用于一种12位250 MSPS流水线ADC,电路采用0.18μm lP5M 1.8 V CMOS工艺实现,测试结果表明该ADC电路在全速采样条件下对于20 MHz的输入信号得到的SNR为69.92 dB,SFDR为81.17 dB,-3 dB带宽达700 MHz以上,整个前端电路的功耗为58 mW.     

一种8位32MS/s的流水线型模数转换器设计

基于电子不停车收费系统(ETC)接收机的要求,在TSMC018μm工艺下设计并实现一种8bit 32 MS/s流水线型模数转换器。通过详细理论分析确定设计参数和电路模型,通过运放共享以及带有增益自举的套筒式运算放大器和开关电容共模反馈电路降低电路的静态功耗,通过动态比较器以及静态锁存结构降低电路的动态功耗,使得功耗降低为原来的一半。测试结果显示ADC输入摆幅-0.4~0.4V下,功耗5.017mA,非使能状态下功耗0.567μA,信噪比(SNR)49.21dB,有效位(ENOB)7.77bit,无杂散噪声(SFDR)65.41dB,面积580μm×450μm。     

一种14位85 MS/s流水线型ADC

基于0.18μm CMOS工艺设计与实现了一种14位85 MS/s流水线型模数转换器(ADC)。采用多种低功耗设计技术来降低系统功耗和面积,包括无采样保持电路前端和运算放大器共享等技术。在无数字校准的条件下,在3.3 V电源电压、85 MHz的时钟频率和70 MHz正弦输入信号频率下,达到了67.9 dBFS的信噪比(SNR)以及82.2 dBFS的无杂散动态范围(SFDR)。该ADC功耗为322 mW,面积为0.6 mm²,适合用于需求低功耗ADC的通信系统中。     

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm² using a 0.18-mum complementary metal oxide semiconductor (CMOS) process     

A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively     

An 8-b 100-MSample/s CMOS pipelined folding ADC

Although cascading reduces the number of folders used in folding analog-to-digital converters (ADCs), it demands wider bandwidth. The pipelining scheme proposed in this work greatly alleviates the wide bandwidth requirement of the folding amplifier. The pipelining is implemented with simple differential-pair folders. The key idea is to use odd multiples of folders with distributed interstage track/holds cooperatively with an algorithm for coding and digital error correction for the nonbinary system. The pipelined folding ADC prototyped using 0.5-μm CMOS exhibits a differential nonlinearity (DNL) of ±0.4 LSB and an integral nonlinearity (INL) of ±1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm×1.2 mm in active area and consumes 165 mW at 5 V     

An 8-bit 12.5-GSample/s SiGe ADC

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm² and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process.     

A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering

Pseudo-random dithers have been used to measure capacitor mismatch and opamp gain errors of the pipelined analog-to-digital converter (ADC) in background and to calibrate them digitally. However, this error measurement suffers from signal range reduction and long signal decorrelation time. A signal-dependent dithering scheme allows the injection of a large dither without sacrificing the signal range and shortens the signal decorrelation time. A 1.5-bit multiplying digital-to-analog converter (MDAC) stage is modified for signal-dependent dithering with two additional comparators, and its capacitor mismatch and gain errors are measured and calibrated as one error. When sampled at 20 MS/s, a 15-bit prototype ADC achieves a spurious-free dynamic range of 98 dB with 14.5-MHz input and a peak signal-to-noise plus distortion ratio of 73 dB with 1-MHz input. Integral nonlinearity is improved from 25 to 1.3 least significant bits (LSBs) after calibrating the first six stages. The chip is fabricated in 0.18-mu CMOS process, occupies an active area of 2.3 x 1.7 mm² , and consumes 285 mW at 1.8 V.     

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channelapplications

The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-μm CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f_in=f _s/2) and sampling frequencies f_s up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f_s /4 over process, temperature, and power-supply variations. At maximum speed (f_s=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f_in=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm² of chip area     

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.     

8位高速低功耗流水线型ADC的设计技术研究

采用7级子ADC流水线结构设计了一个8位80MS/s的低功耗模数转换电路。为减小整个ADC的芯片面积和功耗,改善其谐波失真和噪声特性,重点考虑了第一级子ADC中MDAC的设计,将整个ADC的采样保持电路集成在第一级子ADC的MDAC中,并且采用逐级缩放技术设计7级子ADC的电路结构,在版图设计中考虑每一级子ADC中的电容及放大器的对称性。采用0.18μm CMOS工艺,该ADC的信噪比（SNR）为53dB,有效位数（ENOB）为7.98位,该ADC的芯片面积只有0.56mm2,典型的功耗电流仅为22mA。整个ADC性能达到设计要求。     

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain variation, and slew-rate limiting. The prototype consists of an input sample-and-hold amplifier (SHA) that can serve as a calibration queue, a 12-bit 80-MSample/s pipelined ADC, a digital-to-analog converter (DAC) for calibration, and an embedded custom microprocessor, which carries out the calibration algorithm. The calibration is bootstrapped in the sense that the DAC is used to calibrate the ADC, and the ADC is used to calibrate the DAC. With foreground calibration, test results show that the peak differential nonlinearity (DNL) is -0.09 least significant bits (LSB), and the peak integral nonlinearity (INL) is -0.24LSB. Also, the maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 71.0 and 79.6dB with a 40-MHz sinusoidal input, respectively. The prototype occupies 22.6 mm/sup 2/ in a 0.25-/spl mu/m CMOS technology and dissipates 755 mW from a 2.5-V supply.     

A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process and has a die size of 4mm/spl times/5 mm.     

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply     

An 8-bit, 200 MSPS Folding and Interpolating ADC

An 8-bit, 200 MSPS folding and interpolating analog-to-digitalconverter, ADC, has been implemented in a 1.2 µmBiCMOS-process. It achieves 7.5 effective bits with a power dissipationof 575mW. The active area is 4mm². The implementationand measured results are presented. A simple analytical modelfor the interpolation-induced nonlinearity in a folding and interpolatingADC using sinusoidal folding is presented. The bowing of thereference ladder due to interaction with the input stages isanalyzed, and analytical models are derived.     

A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC

A 7-bit Nyquist folding and interpolating analog-to-digital converter (ADC) that converts at 300 MSamples/s is presented. Using current-mode signal processing techniques for analog preprocessing and a front-end sample-and-hold, the proposed 7-bit folding and interpolating ADC yields a wide input bandwidth up to 60 MHz with six effective number of bits. The ADC consumes 200 mW from a 3.3-V power supply. The chip occupies 1.2 mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.