High-reliability 1.3-μm InP-based uncooled lasers in nonhermeticpackages

We report the first uncooled nonhermetic 1.3-μm InP-based communication lasers that have reliability comparable to their hermetically packaged counterparts for possible applications in fiber in the loop and cable TV. The development of reliable nonhermetic semiconductor lasers would not only lead to the elimination of the costs specifically associated with hermetic packaging but also lead the way for possible revolutionary low-cost optoelectronic packaging technologies. We have used Fabry-Perot capped mesa buried-heterostructure (CMBH) uncooled lasers with both bulk and MQW active regions grown on n-type InP substrates by VPE and MOCVD. We find that the proper dielectric facet passivation is the key to obtain high reliability in a nonhermetic environment. The passivation protects the laser from the ambient and maintains the proper facet reflectivity to achieve desired laser characteristics. The SiO facet passivation formed by molecular beam deposition (MBD) has resulted in lasers with lifetimes well in excess of the reliability goal of 3,000 hours of operation at 85°C/90% RH/30 mA aging condition. Based on extrapolations derived experimentally, we calculate a 15-year-average device hazard rate of <300 FITs (as against the desired 1,500 FITs) for the combination of thermal-and humidity-induced degradation at an ambient condition of 45°C/50% RH. For comparison, the average hazard rate at 45°C and 15 years of service is approximately 250 FITs for hermetic lasers of similar construction. A comparison of the thermal-only degradation (hermetic) to the thermal plus humidity-induced degradation (nonhermetic) indicates that the reliability of these nonhermetic lasers is controlled by thermal degradation only and not by moisture-induced degradation. In addition to device passivation for a nonhermetic environment, MBD-SiO maintains the optical, electrical, and mechanical properties needed for high-performance laser systems     

Reliability test and failure analysis of high power LED packages

A new type application specific light emitting diode(LED) package(ASLP) with freeform polycarbonate lens for street lighting is developed,whose manufacturing processes are compatible with a typical LED packaging process.The reliability test methods and failure criterions from different vendors are reviewed and compared.It is found that test methods and failure criterions are quite different.The rapid reliability assessment standards are urgently needed for the LED industry.85℃/85 RH with 700 mA is used to test our LED modules with three other vendors for 1000 h,showing no visible degradation in optical performance for our modules,with two other vendors showing significant degradation.Some failure analysis methods such as C-SAM,Nano X-ray CT and optical microscope are used for LED packages.Some failure mechanisms such as delaminations and cracks are detected in the LED packages after the accelerated reliability testing.The finite element simulation method is helpful for the failure analysis and design of the reliability of the LED packaging.One example is used to show one currently used module in industry is vulnerable and may not easily pass the harsh thermal cycle testing.     

Compound semiconductor activation energy in humidity

Product reliability investigations typically include accelerated humidity testing. Originally, the “standard” test was a biased 85 °C/85% relative humidity (RH) lifetest for 1000 h. Recently, a substitute accelerated version of this test has been used. The accelerated version is called highly accelerated stress test (HAST). The HAST conditions are also biased, at 130 °C, 85%RH, and approximately 18 PSI overpressure. The duration of the HAST test is normally 96–100 h – to be equivalent to the 85/85 test. This study is intended to investigate thermal acceleration and show that equivalent HAST tests on compound semiconductors are more highly accelerated and could be conducted with much shorter durations.     

Demonstrated reliability of plastic-encapsulated microcircuits formissile applications

For the past decade, overall reliability improvement and product availability have enabled plastic encapsulated microcircuits (PEM) to move from consumer electronics beyond the relatively large and reliability-conscious automotive market, into the military market. Based on the analysis of the worst-case PEM scenario for military applications, demonstrating the moisture reliability under long-term (20 years) dormant storage environments has become the last hurdle for PEM. Studies have demonstrated that PEM can meet the typical missile environments in long-term storage. To further validate PEM reliability in missile applications, Texas Instruments (TI) conducted three separate studies involving 6 years of PEM moisture-life monitoring and assessment, testing of the standard PEM electrical characteristics under the military temperature ranges (-55°C to +125°C), and assessing their robustness in moisture environments after the assembly processes. These TI studies support the use of PEM in missile (or similar) applications. Effective focus on part and supplier selection, supplier teaming, and process monitoring is necessary to maintain the PEM reliability over the required environments at the lowest cost. This paper assesses PEM reliability for a selected missile storage environment using the industry-standard moisture testing, such as biased HAST or 85°C/85%RH (relative humidity), for demonstrating the PEM moisture survivability. The moisture reliability (MTTF) or average moisture lifetime of PEM is assessed to correlate PEM capability to anticipated field-performance environments     

A Study of Accelerated Storage Test Conditions Applicable to Semiconductor Devices and Microcircuits

This preliminary theoretical study on the application of accelerated stress testing for determining storage life of semiconductor devices and microcircuits has resulted in the following conclusions: There are more environmental stresses that can be applied to the accelerated testing of plastic encapsulated microcircuits, than hermetic devices. For hermetic devices, the assurance of initial hermeticity and wire bond integrity should insure long storage-dormancy life. Since only limited storage-dormancy data are available, accelerated testing and verification with use conditions data are necessary to support the conclusion of this study.     

Plastic packages survive where hermetic packages fail

Plastic encapsulation is now a highly reliable method of packaging microelectronics and can be significantly more reliable than military specified “hermetic components” in field deployments of electronics in humid tropical climates. MIL883 hermeticity is an inadequate safeguard against penetration by high levels of moisture in the atmosphere. In this new work, tropical climates are analysed and shown to be significantly more severe than those safeguarded by current MIL883 standards. Field failure returns have revealed that MIL 883 hermetic CerDIP (ceramic dual-in-line) packaged ICs installed in digital switching systems failed catastrophically with a failure rate of 1755 FITs. The cause of failure was severe ingress of moisture, resulting in dewpoints up to 30°C. Alternative indigenous developments of modular digital switches for widespread rural use in India have incorporated plastic encapsulated components selected according to the criteria developed from earlier extensive and successful reliability work by British Telecommunications (BT). Such criteria include the use of HAST (highly accelerated stress technique, invented at BT Labs). The BT Labs pioneering work demonstrated that commercial transfer-moulded epoxy packaged devices from certain sources were more reliable than their hermetic counterparts.Evidence from other published pioneering work has confirmed that plastic packaging now endures as a high reliability method of packaging microelectronics. Such pioneering work is also reviewed in this paper. In the USA, the IEEE Gel Task Force followed the earlier BT Laboratories initiative and concluded that silicone gels are indeed suitable for high reliability applications. AT&T undertook comprehensive materials analyses to show that silicone gels possess remarkably useful properties to safeguard high reliability integrated circuits. CALCE, University of Maryland, conducted studies of simple logic circuits and showed that the achieved reliability in temperature climatic conditions is three times greater than that predicted for military parts. BT Labs continued its work and extended its applicability to optoelectronics. Analyses of MCM applications for satellites by the author also show that plastics are a preferred option. The evidence is that plastic encapsulation is now a very reliable and cost-effective option.     

Qualification of plastic encapsulated microcircuits (PEM) for avionicsBased on ``Plastic Encapsulated Microcircuits (PEM) Qualification Testing'''', by J. A. Scalise, which appeared in the Proceedings of the 46th Electronic Components and Technology Conference, Orlando, FL, U.S.A., 28–31 May 1996, pp. 392–397. © 1996 IEEE.

Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly accelerated stress test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP) and plastic dual-in-line (PDIP).Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by type of compound, passivation (including die coat) and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.     

Sources and control of volatile gases hazardous to hermeticelectronic enclosures

Four gases that threaten operating reliability may be present in hermetic electronic enclosures. Condensates of moisture and/or ammonia can cause metallization corrosion. Hydrogen is a rapid diffuser that can degrade metal-oxide-semiconductor (MOS) device operation. Oxygen can cause oxidation and ensuing failure of solder attachment materials within the sealed package. Other gases, such as carbon dioxide, helium, argon, and organic volatiles are not threats to reliability, but do provide clues to package materials behavior. Knowing sealed package ambient gas composition helps improve materials and processes for hermetic sealing and enables process control to assure reliable products. This paper describes the analysis method for hermetic microelectronics, residual gas analysis (RGA), available at only a few laboratories worldwide. It discusses sealing processes and package piece part materials that are sources of volatiles hazardous to product reliability. It presents materials selection and improvement considerations to reduce and control dangerous volatiles in hermetic packages     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

浅谈IC封装材料对产品分层的影响及改善

IC封装不仅要求封装材料具有优良的导电性能、导热性能以及机械性能,还要求具有高可靠性、低成本和环保性,这也是引线框架、环氧树脂成为现代电子封装主流材料的主要原因,其市场份额约占整个封装材料市场的95%以上。由于环氧树脂封装是非气密性封装,对外界环境的耐受能力较差,尤其是受到湿气侵入时,产品会出现一些可靠性问题,最容易发生的现象是分层。简要分析了框架和环氧树脂对产品可靠性的影响,在此基础上提出一些改善措施。     

无铅倒装焊点的热应力与湿热应力分析

板上倒装芯片（FCOB）作为一种微电子封装结构形式得到了广泛的应用。微电子塑封器件中常用的聚合物因易于吸收周围环境中的湿气而对封装本身的可靠性带来很大影响。文章采用有限元软件分析了潮湿环境下板上倒装芯片下填充料在湿敏感元件实验标准MSL-1条件下（85℃／85％RH、168h）的潮湿扩散分布,进而分别模拟计算出无铅焊点的热应力与湿热应力,并加以分析比较。论文的研究成果不仅对于塑封电子元器件在潮湿环境中的使用具有一定的指导意义,而且对于FCOB器件在实际应用中的焊点可靠性问题具有一定的参考价值。     

Automatically Controlled 2-Vessel Pressure-Cooker Test-Equipment

A highly accelerated humidity test for plastic encapsulated IC reliability short-term evaluation has been studied. 2-Vessel pressure cooker test (PCT) equipment capable of controlling relative humidity and temperature independently, and of keeping specimens free from water droplet condensation, has been designed. This equipment consists of a test chamber and a vapor chamber. Humidity conditions are set by controlling the temperature difference between the test chamber and the vapor chamber. Humidity levels are controlled with the direct pressure adjustment. The whole test chamber is heated in an oven, thereby obtaining temperature stability and uniformity. Using this equipment, humidity tests were carried out on plastic molded ICs. As a result, good test reproducibility and excellent correlation in test results between PCT and conventional humidity test such as 85°C/85%RH, were obtained. As a consequence, it was found possible, in a short time, to evaluate plastic molded IC reliability quantitatively in humidity ambients using this 2-vessel PCT equipment. This equipment can be used for quality assurance testing of plastic-encapsulated ICs in a short time.     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

Intermetallic Formation of Copper Pillar With Sn–Ag–Cu for Flip-Chip-On-Module Packaging

Copper pillar interconnects are a popular interposing option due to the advantages of small pillar size and good thermal and electrical performance, making copper pillar interconnects very useful for high-frequency and high-density flip-chip-on-module (FCOM) packages. However, the challenges associated with the technology include controlling the formation of brittle intermetallic compounds (IMC) and weak interfaces during heat-related processes, and preventing copper migration during bonding and reliability testing. As the reliability of the joint is significantly affected by the property of the surface finish, it is important to understand the influence of different surface finishes on the reliability of copper pillar interconnections. This paper focuses on Ni/Au-capped, Sn-capped, Sn–2.5Ag-capped, and organic solderability preservative (OSP)-capped copper pillar interconnections with lead-free Sn–3.0Ag–0.5Cu solder paste in FCOM packages. The types, morphology, and distribution of IMC formed in the bulk solder, the copper pillar/SAC, and copper pad/ENIG/SAC interfaces during multiple reflows ( 265 $~^{circ}{hbox {C}}$ ) and reliability testing [thermal cycle (TC), autoclave (AC), high-temperature storage (HTS), and thermal shock ([TS)] were investigated using a scanning electron microscope with energy dispersive X-ray (SEM-EDX). The feasibility and reliability of these copper-pillar FCOM systems were also compared and evaluated. The reliability results show that OSP-capped copper pillar interconnects are the best interposing option in terms of reliability and performance.      

Reliability of Complementary MOS Integrated Circuits

This paper describes the results of tests of the stability and reliability of complementary MOS (CMOS) integrated circuits (IC). Operating life-tests at 125°C indicated excellent stability of electrical characteristics of both n-channel and p-channel transistors. Over three million device-hours of accelerated operating life-tests indicated a calculated failure rate, at a 60-percent s-confidence level, of 0.08%/1000 hours at 125°C, which corresponds to 0.01%/1000 hours at 55°C or 0.003%/1000 hours at 25°C. Field-usage reliability data on three satellites in orbit indicate a total failure rate of 0.003%/1000 hours (over thirty-four million operating hours with no failures). The observed failure rates are compared with other available data on IC reliability, and it is concluded that the reliability of CMOS ICs is equal to that of p-channel MOS circuits or of bipolar digital circuits of equal complexity, when each type is prepared by a well-controlled process, and operated at the same temperature. The operating temperature of CMOS IC chips in electronic systems is, however, generally lower since logic functions are accomplished at lower dissipation per gate.     

Reliability evaluation of plastic packaged devices for long life applications by THB test

The reliability of transistors, bipolar and CMOS integrated circuits encapsulated in different types of plastic packages was investigated by using the 85°C/85% R.H. test with applied bias and the results compared with a long term operating life test. Particular attention was devoted to pointing out the influence of technology, process control and working conditions on device reliability and failure mechanisms.In micropackaged transistors the importance of surface passivation in protecting the devices against gold corrosion was forcused, while the need of good process control was confirmed by the results of the test on micropackaged linear integrated circuits.In dual-in-line CMOS integrated circuits silicon nitride and polymide give, in general, a superior protection, but good results were obtained also with normal P-glass passivation when a clever arrangement of layout design rules was adopted. Results obtained exhibit a significant improvement in the reliability of plastic packaged devices, with the best figures showing no failures after 15,000 hours at 85°C/85% R.H. test with bias.     

Long-term reliability of Ti–Pt–Au metallization system for Schottky contact and first-level metallization on SiC MESFET

The stability of metal layers on semiconductors is a key issue for the device electrical performances. Therefore, the reliability of SiC/Ti/Pt/Au system was investigated using storage steady-stress testing, AES (Auger Electron Spectrometry), and SIMS (Secondary Ions Mass Spectrometry) analysis. The study was conducted on different patterns for gate and interconnection structure to underline the different reliability problems. Auger and SIMS analysis showed important modifications in the three-metal structure without reactions with the SiC substrate. The resistance degradation was assigned to interdiffusion phenomena. It was analyzed with a diffusion-controlled model. Activation energies and mean time to failure (MTF) were calculated for a failure criterion defined as a 10% increase of the resistance. Finally, the different rules of the metallization degradation in MESFET behaviours for interconnections and gate were discussed.     

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.     

长期贮存对气密性封装的影响研究

密封微电子器件在对可靠性要求较高领域占有绝对的地位,为了研究长期室内自然贮存对密封微电子封装性能的影响,对贮存在北京某研究所库房的多种气密性封装微电子器件进行试验分析。运用破坏性物理分析(DPA)方法检验样品的密封性、内部形貌、键合强度和芯片粘贴强度等,总结出长期贮存对气密性封装器件封装性能影响的结论;并根据密封性测试结果对器件分组,分别得到密封合格与不合格产品长期贮存后封装性能的实测数据,对密封性能对元器件贮存可靠性的影响进行研究,为元器件的筛选和贮存提供借鉴。     

Process reliability screening in situ

A critical element of process technology development is reliability and consequently reliability testing. Environmental stress tests such as Unbiased Highly Accelerated Stress Test (UHAST), Temperature Humidity Bias (THB), Thermal Cycling and High Temperature Storage (HTS) are traditionally performed on sample products or standard product-like qualification vehicles when introducing a new process technology. Because of the long cycle time for assembly and reliability stressing, these tests are not typically performed as part of the development cycle. This paper describes the use of HTS and UHAST at the wafer level to evaluate a new backend process currently in development.