一种端口速率可变的共享存储器交换

针对局域网和城域网中的多种数据传输速率结构,该文提出了一种共享存储器交换结构,在普通共享存储器交换结构的基础上,对支持可变的端口速率,以及支持变长数据包交换进行了改进,所提出的交换结构还具有自同步特点,即各输入输出端口之间不需要全局同步;同时还考虑了对变长数据包的队列管理。     

A Polymer‐Electrolyte‐Based Atomic Switch

Studies on a resistive switching memory based on a silver‐ion‐conductive solid polymer electrolyte (SPE) are reported. Simple Ag/SPE/Pt structures containing polyethylene oxide–silver perchlorate complexes exhibit bipolar resistive switching under bias voltage sweeping. The switching behavior depends strongly on the silver perchlorate concentration. From the results of thermal, transport, and electrochemical measurements, it is concluded that the observed switching originates from formation and dissolution of a silver metal filament inside the SPE film caused by electrochemical reactions. This is the first report of an electrochemical “atomic switch” realized using an organic material. The devices also show ON/OFF resistance ratios greater than 10⁵, programming speeds higher than 1 μs, and retention times longer than 1 week. These results suggest that SPE‐based electrochemical devices might be suitable for flexible switch and memory applications.     

A Shared Buffer Memory ATM Access Switch

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PERFORMANCE COMPARISON OF CELL－BASED AND PACKET－BASED SWITCHING SCHEMES FOR SHARED MEMORY SWITCHES

Shared Memory (SM) switches are widely used for its high throughput,low delay and efficient use of memory.This paper compares the performance of two prominent switching schemes of SM packet switches:Cell-Based Switching (CBS) and Packet-Based Switching (PBS).Theoretical analysis is carried out to draw qualitative conclusion on the memory requirement,throughput and packet delay of the two schemes.Furthermore,simulations are carried out to get quantitative results of the performance comparison under various system load,traffic patterns,and memory sizes.Simulation results show that PBS has the advantage of shorter time delay while CBS has lower memory requirement and outperforms in throughput when the memory size is limited.The comparison can be used for tradeoff between performance and complexity in switch design.     

Dynamic buffer management using per‐queue thresholds

Shared buffer switches consist of a memory pool completely shared among output ports of a switch. Shared buffer switches achieve low packet loss performance as buffer space is allocated in a flexible manner. However, this type of buffered switches suffers from high packet losses when the input traffic is imbalanced and bursty. Heavily loaded output ports dominate the usage of shared memory and lightly loaded ports cannot have access to these buffers. To regulate the lengths of very active queues and avoid performance degradations, threshold‐based dynamic buffer management policy, decay function threshold, is proposed in this paper. Decay function threshold is a per‐queue threshold scheme that uses a tailored threshold for each output port queue. This scheme suggests that buffer space occupied by an output port decays as the queue size of this port increases and/or empty buffer space decreases. Results have shown that decay function threshold policy is as good as well‐known dynamic thresholds scheme, and more robust when multicast traffic is used. The main advantage of using this policy is that besides best‐effort traffic it provides support to quality of service (QoS) traffic by using an integrated buffer management and scheduling framework. Copyright © 2006 John Wiley & Sons, Ltd.     

Ovonic Memory Switching in Multimaterial Fibers

We demonstrate the first rewritable memory in thermally drawn fibers. A high tellurium‐content chalcogenide glass, contacted by metallic electrodes internal to the fiber structure, is drawn from a macroscopic preform. An externally applied voltage is utilized to switch between a high resistance (OFF) and a low resistance (ON) state; this in turn allows the fibers to function as a memory device reminiscent of the ovonic switch. The difference between the ON and OFF states is found to be four orders of magnitude. The glass–crystal phase transition is localized to micrometer‐wide filaments, whose position can be optically controlled along the fiber axis. An architecture that enabled the encoding of multiple bits per fiber is described.     

应用于FRAM的集成铁电电容的研究

集成铁电电容的制备是铁电存储器的关键工艺之一。该文采用射频(RF)磁控溅射法在Pt/Ti/SiO2/Si制备Pb(Zr,Ti)O3(PZT)薄膜,上下电极Pt采用剥离技术工艺制备,刻蚀PZT薄膜,形成Pt/PZT/Pt/Ti/SiO2/Si集成电容结构,最后高温快速退火。结果表明,这种工艺条件可制备性能良好的铁电电容,符合铁电存储器对铁电电容的要求。     

一种基于FLATCELL结构的MASKROM芯片设计

文章介绍了一种高密度的掩模式只读存储器CMOS集成电路及其工作原理,它所采用的是平坦式离子植入绝缘工艺的存储单元结构,能使电路在有限的面积内获得较高的集成密度。重点讨论存储单元的物理原理和逻辑结构,相应的外围电路模块的电路设计与功能实现。     

Novel Authentic and Ultrafast Organic Photorecorders Enhanced by AIE-Active Polymer Electrets via Interlayer Charge Recombination

Organic photonic memory, featuring a variety of glamorously light-driven characteristics, is rapidly growing into an indispensable building block for next-generation optical communication systems. However, the ambiguity of their operating mechanism associated with the limitation of photoadaptive materials as an electronics promoter results in the slow development of photonic transistor-based devices. In this study, the conjugated polymers composed of donor–acceptor motifs with typical aggregation-induced emission (AIE) behaviors are designed and successfully discover high-performance photoprogrammable memory. Moreover, the mechanism of photoboosted recording behavior, attributed to the recombination of the formed interlayer excitons right after simultaneous excitation without applying vertical and parallel electric-field at the interface in-between active semiconductor and AIE polymers, is cautiously corroborated by steady-state PL and pulse PL measurements. The AIE-polymer memory devices perform ultrafast photoresponse time of 0.1 ms, an outstanding current switch ratio up to 10⁶, and retention stability over 40 000 s without significant dissipation. Furthermore, photoresponsive AIE-polymer electrets not only modulate the memory performance through the emission wavelength but easily switch storage behavior of nonvolatile memory from flash to WORM by adjusting the torsion-angle through the motif of the donor and acceptor moieties. These findings open an avenue for designing conjugated polymer electret for ultrafast optical storage devices.     

The Light-Emitting-Switch Integrated-Circuit Display

A semiconductor display device utilizing arrays of light-emitting devices with inherent memory has been developed. The central element is a p-i-n device that exhibits current-controlled negative resistance and emits light in the high-conductance state. This light-emitting and switching device has been employed in a monolithic integrated circuit that permits the logic function in addition to the opticaf output function to be perfomed on the display surface. The circuit has been developed in a configuration that permits matrix address. This paper discusses the basic light-emitting switch and its utilization as a matrix display device and describes the development of an integrated structure employing the light-emitting switch and its incorporation into a complete display system. Modifications and improvements of the matrix display system based on this concept are also discussed.     

一种输入输出排队交换机中分布式分组调度方法的研究

针对采用共享缓存(shared memory)做为交换机构(switching fabric)的输入输出排队交换机,该文给出了一个分布式分组调度方法DHIOS(Distriduted Hierarchical Ingress and OutputScheduling)并做了详细的仿真。表明DHIOS可以支持变长分组,能够确保业务流的QoS,性能优良。     

Phase change materials and their application to random access memory technology

Phase change materials can exist in two different phases, the amorphous and the crystalline phase, which exhibit distinctly different physical properties. It is possible to repeatedly switch the state of these materials, from the amorphous phase to the crystalline phase by heating the material above its crystallization temperature, and from the crystalline to the amorphous phase by melt-quenching. Phase change materials have been utilized very successfully in all modern optical re-writable storage media such as CDs, DVDs and Blu-ray disks. Recently, they have also been applied to solid-state memory devices where their large difference in electrical resistivity is used to store information. This paper reviews the unique properties of phase change materials in particular as they are important for their application to these devices.     

A Die‐Selection Method Using Search‐Space Conditions for Yield Enhancement in 3D Memory

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions.     

基于FPGA和USB的64路数据采集系统设计

提出了一种基于FPGA和USB的高速数据传输、存储及显示系统的设计及实现,并对其中的FPGA功能模块以及USB传输模块等进行了介绍.该系统不但可以快速方便地传输、存储及显示数据,还具有判断防止数据错位的功能.     

Noncontact All-In-Situ Reversible Reconfiguration of Femtosecond Laser-Induced Shape Memory Magnetic Microcones for Multifunctional Liquid Droplet Manipulation and Information Encryption

Shape memory polymers can change their shapes in a controlled way under external stimuli and thus promote the development of smart devices, soft robotics, and microfluidics. Here, a kind of iron particles (IPs) doped shape memory microcone is developed for noncontact all-in-situ reversible tuning between the tilted and upright state under near-infrared (NIR) irradiation and magnetic field (MF) actuation. The magnetic microcones are simply fabricated by a laser-ablated replica-molding strategy so that their height can be precisely controlled by adjusting the laser machining parameters. In addition, it is found that the droplets can be transported unidirectionally on the tilted microcones, which is related to the variation of the adhesion force induced by the length of the triple contact line (TCL). Finally, other multifunctional applications have also been realized, such as, selective droplet release, information encryption, rewritable display, and reusable temperature switch. This work may provide a facile strategy for developing multiresponsive smart devices based on shape memory polymers.     

Gigabit Ethernet switches using a shared buffer architecture

Gigabit Ethernet networks have seen great demand in recent years. This growth was fueled by both an increase in port speed at the client side and new applications in MAN and WAN space. In this article, we report a highly integrated Ethernet switch IC design that supports 12 gigabit ports and one 10 Gb port. All packet memory and search memory are integrated on chip. A deeply pipelined structure with parallel memory access is employed to achieve wirespeed search performance. A flexible policy engine is designed to allow packet filtering and modification. A novel tail buffer architecture is proposed to address the variable packet length issue in the shared buffer architecture. Custom mixed-signal circuits are incorporated to implement the 10G Ethernet interface in XGMII. The chip integrates 70 million transistors in a 16 mm /spl times/ 15 mm die using 0.18 /spl mu/m CMOS technology. The chip has been tested to verify the wirespeed searching and switching performance.     

Room‐Temperature Nonvolatile Memory Based on a Single‐Phase Multiferroic Hexaferrite

The cross‐coupling between electric polarization and magnetization in multiferroic materials provides a great potential for creating next‐generation memory devices. Current studies on magnetoelectric (ME) applications mainly focus on ferromagnetic/ferroelectric heterostructures because single‐phase multiferroics with strong magnetoelectric coupling at room temperature are still very rare. Here a type of nonvolatile memory device is presented solely based on a single‐phase multiferroic hexaferrite Sr₃Co₂Fe₂₄O₄₁ which exhibits nonlinear magnetoelectric effects at room temperature. The principle is to store binary information by employing the states (magnitude and sign) of the first‐order and the second‐order magnetoelectric coefficients (α and β), instead of using magnetization, electric polarization, and resistance. The experiments demonstrate repeatable nonvolatile switch of α and β by applying pulsed electric fields at room temperature, respectively. Such kind of memory device using single‐phase multiferroics paves a pathway toward practical applications of spin‐driven multiferroics.     

嵌入式存储器内建自测试的原理及实现

随着集成电路设计规模的不断增大 ,在芯片中特别是在系统芯片 SOC( system on a chip)中嵌入大量存储器的设计方法正变得越来越重要。文中详细分析了嵌入式存储器内建自测试的实现原理 ,并给出了存储器内建自测试的一种典型实现。     

一种共享存储交换结构中的双门限队列控制策略

传统的共享存储交换结构的门限控制算法通常以当前各个队列长度为依据,缺乏对网络节点设备全局流量场景的考虑,且对组播的支持不足.本文提出使用有效业务量作为控制各个端口队列门限的主要依据,让各个端口承担相同的流量压力,从而使系统保持均衡状态.在经典的有效带宽理论的基础上,结合输入流量速率和分配的缓冲区大小一起来定义输出端口的有效业务量,给出了"缓存换带宽"的计算公式,对流量压力进行准确度量.双门限的使用使得共享存储空间既能够保持在平均意义下的平衡,又能实现突发时段的调剂.进一步,对组播信元的转发也可以纳入这个算法框架.模拟结果显示,在不同的流量模式下,这个算法比传统动态门限算法在取典型值α=1和组播浓度为30%时,对芯片的使用效率和端口的公平性分别提高15%和25%以上.     

基于解析电导率模型的相变存储器SPICE模型

在相变存储器的外围电路设计中,相变存储单元的电路模型是连接器件与电路的桥梁。在本文中,提出了一种基于解析电导率模型的相变存储器电路模型,与前面的工作相比,该模型利用解析电导率模型代替了使用传统模型中需要利用测试结果建模的缺点,可以通过材料的参数计算相变存储单元的电阻,能够反映相变材料中的载流子传输特性。同时,基于等温假设,提出了解析温度模型,并基于JMA方程建立的相变动力学模型,结果表明,该模型能够进行相变存储单元瞬态与稳态电路仿真,并与测试结果符合较好。