用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

基于802.11a协议的无线局域网低噪声放大器和改进的有源双平衡混频器

提出了采用0.18μm CMOS工艺,应用于802.11a协议的无线局域网接受机的低噪声放大器和改进的有源双平衡混频器的一些简单设计概念。通过在5.8 GHz上采用1.8 V供电所得到的仿真结果,低噪声放大器转换电压增益,输入反射系数,输出反射系数以及噪声系数分别为14.8 dB,-20.8 dB,-23.1 dB和1.38 dB。其功率损耗为26.3 mW。设计版图面积为0.9 mm×0.67 mm。混频器的射频频率,本振频率和中频频率分别为5.8 GHz,4.6 GHz和1.2 GHz。在5.8 GHz上,混频器的传输增益,单边带噪声系数（SSB NF）,1 dB压缩点,输入3阶截点（IIP3）以及功率损耗分别为-2.4 dB,12.1 dB,3.68 dBm,12.78 dBm和22.3 mW。设计版图面积为1.4 mm×1.1 mm。     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

5.6GHz CMOS低噪声放大器设计

分析了一种射频COMS共源-共栅低噪声放大器的设计电路,采用TSMC 90nm低功耗工艺实现。仿真结果表明:在5.6GHz工作频率,电压增益约为18.5dB;噪声系数为1.78dB;增益1dB压缩点为-21.72dBm;输入参考三阶交调点为-11.75dBm。在1.2V直流电压下测得的功耗约为25mW。     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

1.8GHz 0.35mm CMOS低噪声放大器的实现

介绍了一种频率为1.8GHz的低噪声放大器(LNA)的设计方案,采用TSMC 0.35μm CMOS工艺实现,增益为25dB,噪声系数2.56dB,功耗≤10mW,IIP3为-25dB或5dBm。     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

Design of a Sub-mW 960-MHz UWB CMOS LNA

This paper presents a sub-mW ultra-wideband (UWB) fully differential CMOS low-noise amplifier (LNA) operating below 960 MHz for sensor network applications. By utilizing both nMOS and pMOS transistors to boost the transconductance, coupling the input signals to the back-gates of the transistors, and combining the common-gate and shunt-feedback topologies, the LNA achieves 13 dB of power gain, a 3.6 dB minimum noise figure, and -10 dBm of IIP3 with only 0.72 mW of power consumption from a 1.2 V supply     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 $muhbox{m}$ CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under ${- 9}~{rm dB}$ in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 ${rm mm}^{2}$.      

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.