A New Scan Partition Scheme for Low‐Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.     

NoC‐Based SoC Test Scheduling Using Ant Colony Optimization

In this paper, we propose a novel ant colony optimization (ACO)‐based test scheduling method for testing network‐on‐chip (NoC)‐based systems‐on‐chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test‐access‐mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC’02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.     

High‐Performance Low‐Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.     

Integrated Rail‐to‐Rail Low‐Voltage Low‐Power Enhanced DC‐Gain Fully Differential Operational Transconductance Amplifier

In this paper, we present an integrated rail‐to‐rail fully differential operational transconductance amplifier (OTA) working at low‐supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand‐by power dissipation (lower than 0.17 mW in the rail‐to‐rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 μm), presents a 37 V/μs slew‐rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

Low‐Power Cool Bypass Switch for Hot Spot Prevention in Photovoltaic Panels

With the introduction of high‐current 8‐inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In this paper, we present the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. This enables its integration, even directly on the panel, thereby opening new scenarios for next generation PV systems.     

Random Walk Guided Decap Embedding for Power/Ground Network Optimization

The reliability of power/ground networks is becoming significantly important in modern integrated circuits, while decap insertion is a main approach to enhance the power grid safety. In this brief, we propose a fast and efficient decap allocation algorithm, and adequately consider the leakage effect of decap. This approach borrows the idea of random walks to perform circuit partitioning and does subsequent decap insertion based on locality property of partitioned area, which avoids solving a large nonlinear programming problem in traditional decap optimization process. The optimization flow also integrates a refined leakage current model for decaps which makes it more practical. Experimental results show that our proposed method can achieve approximate 15 X speed up over the optimal budget method within the acceptable error tolerance. Also this algorithm only causes a few penalty area to compensate the leakage effect.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.     

基于整体退火遗传算法的低功耗极性转换

针对n变量逻辑函数在不同极性下所对应REED-MULLER(RM)电路功耗和面积不问的特点,对信号几率传递算法、多输入XOR/AND(异或/与)门的低功耗分解算法和多成份极性转换算法进行了深入研究,成功地将整体退火遗传算法(whole annealing genetic algorithm,WAGA)应用于RM电路最佳极件的搜索.通过对8个MCNC Benchmark测试表明,算法搜索到的最佳极性,其所对应RM电路的SYNOPSYS综合结果,与极性0时相比,功耗、面积和最大延时的平均节省分别达到了77.2%,62.4%和9.2%.     

基于整体退火遗传算法的低功耗极性转换

针对n变量逻辑函数在不同极性下所对应REED-MULLER(RM)电路功耗和面积不问的特点,对信号几率传递算法、多输入XOR/AND(异或/与)门的低功耗分解算法和多成份极性转换算法进行了深入研究,成功地将整体退火遗传算法(whole annealing genetic algorithm,WAGA)应用于RM电路最佳极件的搜索.通过对8个MCNC Benchmark测试表明,算法搜索到的最佳极性,其所对应RM电路的SYNOPSYS综合结果,与极性0时相比,功耗、面积和最大延时的平均节省分别达到了77.2%,62.4%和9.2%.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit‐parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application‐specific integrated circuit and field‐programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.     

A Low‐Voltage High‐Performance CMOS Feedforward AGC Circuit for Wideband Wireless Receivers

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling‐time constraints. This makes the use of traditional closed‐loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast‐settling response. The AGC has been implemented in a 0.35 μm standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 μs.     

Traffic grooming and clique partitioning‐based spectrum assignment in elastic optical networks

We adopt a fragmentation reducing policy for spectrum assignment and incorporate it with multicast traffic grooming in EON. To reduce fragmentation, the spectrum is partitioned based on the clique partitioning approach and spectral slots are assigned to traffic demands depending on which partition they belong. Simulation results predict that the proposed approach has better spectrum slot utilization compared to the state‐of‐the‐art non‐partitioning approach and the proposed approach reduces fragmentation, and also has less blocking ratio compared to the state‐of‐the‐art partitioning approach.     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.     

On‐Chip Bus Serialization Method for Low‐Power Communications

One of the critical issues in on‐chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low‐power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word‐to‐word and bit‐by‐bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG‐4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost‐effective when implemented as a hardware circuit since its algorithm is very simple.     

Novel Low‐Power High‐dB Range CMOS Pseudo‐Exponential Cells

In this paper, novel CMOS pseudo‐exponential circuits operating in a class‐AB mode are presented. The pseudo‐exponential approximation employed is based on second order equations. Such terms are derived in a straightforward way from the inherent nonlinear currents of class‐AB transconductors. The cells are appropriate to be integrated in portable equipment due to their compactness and very low power consumption. Measurement results from a fabricated prototype in a 0.5 μm technology reveal a range of 45 dB with errors lower than ±0.5 dB, a power consumption of 100 μW, and an area of 0.01 mm².     

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.