Digital integrator design using Simpson rule and fractional delay filter

The IIR digital integrator is designed by using the Simpson integration rule and fractional delay filter. To improve the design accuracy of a conventional Simpson IIR integrator at high frequency, the sampling interval is reduced from T to 0.5T. As a result, a fractional delay filter needed to be designed in the proposed Simpson integrator. However, this problem can be solved easily by applying well-documented design techniques of the FIR and all-pass fractional delay filters. Several design examples are illustrated to demonstrate the effectiveness of the proposed method.     

用于高频的新颖开关电容积分器

本文研究了用于开关电容(SC)滤波器的离散积分器,所推荐的积分器是由无耗离散积分器(LDI)和双线性离散积分器的最佳线性结合而成,因此,称之为组合离散积分器(CDI)。由于这个积分器使正常转折频率增加一倍,并使高频离散积分器误差减少到最低限度,所以它对高频应用是理想的。文中给出了组合离散积分器的几种SC实现,并且还给出了以组合离散积分器为基础,模拟一般一阶和二阶的模拟滤波器单元的SC电路。     

双极点滤波器组:一种新的非相参积累器

 本文提出了一种新的非相参积累器——双极点滤波器组.它比传统双极点滤波器具有更高的稳定性,更低的滤波器系数灵敏度.因而双极点滤波器组是一种稳健的积累器.此外,它与双极点滤波器具有相同的运算量和几乎相同的性能.所以,双极点滤波器组具有较好的实用性.     

A feedforward excess-phase cancellation technique for integrators

Integrators are useful analogue function blocks. A representative application of integrators is a continuous-time filter on an integrated circuit. Excess phase shift of integrators is one of the most severe problems, because excess phase shift at the unity gain frequency degrades the frequency characteristics of the filters. This paper describes a feedforward excess-phase cancellation technique. The proposed technique is applied to integrators which have feedback with an amplifier. The proposed idea is verified by experiment. It is shown that the excess-phase shift due to the gain-bandwidth product of operational amplifiers is cancelled. The proposed technique is useful for realization of integrated continuous-time filters using integrators because extra capacitors are unnecessary. An integrator with the excess-phase cancellation and a third-order leapfrog filter using the integrator are designed and demonstrated by HSPICE simulation. The integrator has a parasitic pole whose frequency is proportional to the unity gain frequency. The simulation results show that the phase characteristics are improved by the proposed technique over the wide range of the unity gain frequency.     

Double‐Sharpened Decimation Filter Employing a Pre‐droop Compensator for Multistandard Wireless Applications

This paper presents a double‐sharpened decimation filter based on the application of a Kaiser and Hamming sharpening technique for multistandard wireless systems. The proposed double‐sharpened decimation filter uses a pre‐droop compensator which improves the passband response of a conventional cascaded integrator‐comb filter so that it provides an efficient sharpening performance at half‐speed with comparison to conventional sharpened filters. In this paper, the passband droop characteristics with compensation provides –1.6 dB for 1.25 MHz, –1.4 dB for 2.5 MHz, –1.3 dB for 5 MHz, and –1.0 dB for 10 MHz bandwidths, respectively. These results demonstrate that the proposed double‐sharpened decimation filter is suitable for multistandard wireless applications.     

一种基于平衡式对数域积分器的高阶滤波器

提出了一个新的工作在甲乙类状态的平衡式对数域积分器 ,用跨导线性原理分析得到其传递函数。基于该积分器电路 ,采用无源网络模拟法设计出一个 1 d B波纹的五阶切比雪夫对数域低通滤波器。PSpice仿真结果表明 ,这种新型对数域滤波器能在低电压条件下工作 ,并具有高频、宽调谐范围和低失真等特点。     

改进型跳耦结构电流镜滤波器

提出了一种利用电流镜积分器和微分器实现的改进型跳耦结构滤波器,讨论并比较了跳耦结构和改进型跳耦结构滤波器的设计方法,改进方法突破了单纯用电流镜积分器实现滤波器的局限,简化了椭圆函数滤波器的信号流图和电路结构;完成了MOS级的计算机仿真,仿真结果表明所提出的电路方案正确有效。     

应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

以ⅡR滤波器作补偿的CIC滤波器设计

为解决积分梳状(CIC)滤波器通带失真大和阻带衰减小对其应用的限制,在分析传统CIC滤波器幅频特性的基础上,给出一种用二阶ⅡR滤波器作为补偿滤波器级联CIC滤波器的改进方法。仿真结果表明,它与同级数规模的内插二阶多项式CIC滤波器、锐化CIC滤波器(SCIC)相比,通带和阻带的性能得到较大改善,实现复杂度较低。因此,它适用于对通带、阻带性能和实现复杂度要求较高的多采样率转换系统。     

A Miniaturized Bandwidth Reconfigurable Bandpass Chip Filter with Semi-lump ed Topology and GaAs pHEMT Technology

A miniaturized reconfigurable bandpass chip filter with semi-lumped topology and Gallium Arsenide pseudomorphic High electron mobility transistor (GaAs pHEMT) technology is proposed. Semi-lumped topology is employed to instead the traditional lumped inductor with microstrip transmission line, which can reduced the size of the tunable filter significantly. Three-order series and shunt resonated bandpass filter is implemented with shorted stubs and metal-insulator-metal capacitors. Two transmission zeros are introduced with the series resonator and the shunted GaAs FET. By tuning the gate bias circuit of the FET, the capacitance of the series resonator is changed and the bandwidth of the filter is adjusted correspondingly. An equivalent circuit model is developed to interpret the mechanism of the proposed filter circuit. A reconfigurable on chip filter sample operated at 10GHz is fabricated to validate the design. Two fractional bandwidth of 14.3％and 23.5％are tuned with bias voltage of the FET, while insertion loss of 2.4dB and 2.2dB are observed with the filter, respectively. The area of the chip filter is 0.86 × 0.96mm2 and is equivalent to an electrical length of 0.08 × 0.09λg2 at center frequency. Measurement results agree well with the simulation ones.     

多输出端电流模式全差分积分器实现二阶带通滤波器

提出了用多输出端电流模式全差分积分器(MCDI)实现二阶带通滤波器的方法。分析了输入级为PMOS管的MCDI及所提出的滤波器的特性，由该类型积分器所构成的滤波器，不仅具有较高的信噪比性能，而且能达到通过调节积分器的偏置电流值的大小能使得其所构成的带通滤波器的中心频率可在很宽的范围内调控的目的。应用台积电(TSMC)2层多晶硅、4层金属(2P4M)混合信号(mixed-mode signal)3．3V电源电压、0．35μ m、CMOS工艺参数仿真得到的带通滤波器的功耗仅为0．28mW左右，仿真结果表明滤波器设计正确、有效。     

First-order, switched-capacitor, low-pass filter implemented with GaAs insulated-gate FET switches

The application of the GaAs insulated-gate FET in switched-capacitor circuits is demonstrated. This is achieved by constructing a first-order, switched-capacitor, low-pass filter from monolithic GaAs IGFET switches and discrete capacitors. Hysteresis in the FET characteristic is shown to be unimportant. FET switching is shown to be independent of the absolute level of the switching signal.<>     

用对数域电流模式积分器实现的高频集成滤波器

文本提出了全差动对数域电流模式积分器．该积分器的时间常数受参考偏流控制,其直流增益可达60dB,在高频它具有比较平坦的相频特性。用该积分器设计的二阶滤波器和1dB波纹五阶Chebyshev低通滤波器,计算机仿真显示,“实际”频响特性几乎是理想的．且频率可在很宽的范围内调控．这种滤波器具有很低的THD。     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

用AOA设计有源补偿双二阶电流模式滤波器

为获得高频率、高精度双二阶电流模式滤波器,根据实际伴随运算放大器(AOA)的开环频率特性,先分析了实际AOA积分器的频率特性,后分析了有源补偿的AOA积分器的频率特性。再借助于拆环法,通过巧妙设计,给出了AOA有源补偿双二阶电流模式滤波器。最后采用预失真技术,使该电路的实际参数与设计值完全吻合。计算机仿真表明,所提出的电路正确有效。     

对数域积分电路的分析与应用

本文分析了一种对数域积分电路的特性,以及极间电容对其性能的影响.在此基础上给出了一般对数域滤波器的设计方法,以及其在宽频带的流控振荡器(ICO)和锁相环电路中的应用,并给出了模拟结果.     

适宜集成的KHN滤波器设计

为了获得高精度的电压模KHN滤波器,以Deboo积分器为原型,先给出一种高精度、易集成的变形Deboo积分器,再借助Meson公式,用变形Deboo积分器设计出极点频率为31.8 kHz、品质因素为1、通带增益为2的通用电压模KHN滤波器.该电路不仅可同时实现高通、带通和低通输出,且极点频率与品质因素能实现正交、精确调节,电路的参数取决于电阻比,两积分电容接地,因而适合单片集成技术.计算机仿真结果与理论分析一致.     

A tunable filter using amplifier pole

A circuit consisting of two periodically operated switches, potentiometers, resistors, and compensated operational amplifiers, but not containing external capacitors, is proposed for the realization of a second-order bandpass and low-pass filter. The filter is electronically tunable and the natural frequency of the filter varies linearly with the width of the pulses controlling the FET switches.